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Output capacitance ( $C_{{\mathrm {OSS}}}$ ) hysteresis has recently been discovered as a new source of power loss in resonant converters with advanced superjunction (SJ) FETs. This brief unveils the physical mechanism responsible for $C_{{\mathrm {OSS}}}$ hysteresis by means of mixed-mode simulations. A new physical effect, based on stranded charges, is observed in the SJ-FETs processed by multi-implant multiepitaxy with small cell pitch. The alternative trench-filling epitaxial growth is a process suitable to address the resonant converters due to its inherent immunity to the $C_{{\mathrm {OSS}}}$ hysteresis. [ABSTRACT FROM AUTHOR]

In this paper, the third quadrant behavior of a high-voltage superjunction mosfet (SJ-FET) in cascode configuration (CC) with a low-voltage silicon mosfet is deeply studied by means of an analytical model and experimental data. The third quadrant dynamic behavior of the SJ-CCs is compared to the standalone counterparts by evaluating their reverse recovery time (tRR), reverse recovery peak current (IRRM), and reverse recovery charge (QRR). An analytical model and experimental results show that the SJ-CC avoids or mitigates the activation of the SJ-FET body diode during the third quadrant operation. As a consequence, the SJ-CC strongly improves the widely used figure-of-merit RON·QRR, which considers the on-state resistance of the transistors (RON). In addition, the results obtained using an SJ-CC are similar or better than those achieved by SJ-FETs with enhanced reverse recovery (i.e., irradiated SJ-FETs). This paper also includes a comparison with commercial wide bandgap switches, concluding that the RON·QRR value provided by the SJ-CC is around eight times higher than that provided by a commercial GaN cascode. [ABSTRACT FROM AUTHOR]

Superjunction MOSFETs in cascode configuration with low-voltage silicon MOSFETs are evaluated in this paper. The proposed structure combines the good switching performance provided by the cascode configuration with the benefits of the silicon technology such as its robustness, maturity, and low cost. This paper aims to explain and to demonstrate the reduction of switching losses of superjunction MOSFETs in cascode configuration with respect to their standalone counterparts (directly driven). A detailed simulation analysis of power loss contributions is carried out under hard-switching operation. Moreover, experimental evidence is provided using a boost converter (100–400 V) operating in continuous conduction mode for different switching frequencies (100–400 kHz) and output power levels (180–500 W). [ABSTRACT FROM AUTHOR]

A new analytical model is presented in this study to predict power losses and waveforms of high-voltage silicon superjunction MOSFET during hard-switching operation. This model depends on datasheet parameters of the semiconductors, as well as the parasitics obtained from the printed circuit board characterization. It is important to note that it also includes original features accounting for strong capacitive nonlinearities and displacement currents. Moreover, these features demand unusual extraction of electrical characteristics from regular datasheets. A detailed analysis on how to obtain this electrical characteristic is included in this study. Finally, the high accuracy of the model is validated with experimental measurements in a double-pulse buck converter setup by using commercial SJ MOSFET, as well as advanced device prototypes under development. [ABSTRACT FROM PUBLISHER]