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46 results on '"Belhaire, Eric"'

2. Power and area optimization for run-time reconfiguration system on programmable chip based on magnetic random access memory

Author

Zhao, Weisheng, Belhaire, Eric, Chappert, Claude, and Mazoyer, Pascale

Subjects
MRAM (Computer memory) -- Design and construction, MRAM (Computer memory) -- Properties, Integrated circuits -- Design and construction, Integrated circuits -- Usage, Semiconductor chips -- Design and construction, Semiconductor chips -- Usage, Digital integrated circuits -- Research, Switching circuits -- Research, Standard IC, Programmable logic array, Business, Electronics, Electronics and electrical industries
Abstract

In recent years, magnetic random access memory (MRAM) based run-time system on programmable chip (SOPC) has been proposed as a solution to the critical drawbacks of current field programmable gate arrays (FPGAs), such as long (re)boot latency, high standby power, and limits for run time reconfiguration. However, the integration of MRAM in FPGA circuits brings its own problems, including large die area and high dynamic power for the switching circuit. In this paper, we present some solutions to overcome the power and area constraints and thereby improve the performance of MRAM based SOPC. We have done simulations and calculations based on the STMicroelectronics 90 nm design kit and a complete magnetic tunnel junction model. Index Terms--Flip-flop, FPGA, low power and low die area, LUT, MRAM, nonvolatile, run-time reconfiguration, SOPC.

Published
2009

4. VHDL simulation of magnetic domain wall logic

Author

Klein, Jacques-Olivier, Belhaire, Eric, Chappert, Claude, Cowburn, Russel P., Petit, Dorothee, and Read, Dan

Subjects
Electromagnetism -- Research, Business, Electronics, Electronics and electrical industries
Abstract

The VHSIC hardware description language (VHDL) simulation of domain wall logic allows to validate magnetic circuits functionality early in the design stage. In this paper, we present two VHDL simulation techniques for domain wall (DW) logic. The first one, closer to the physics, uses models of components described at the behavioral level. It allows to study the basic functions and reveals the specificities of DW logic. The second one, closer to the logic, models components with logic gates and delays and it allows very fast simulation of complex circuits. Index Terms--Circuit simulation, digital simulation, magnetic logic devices.

Published
2006

8. Réduction du recouvrement dans une caméra plénoptique 2.0

Author

Cossu, Kevin, Druart, Guillaume, Chambon, Mathieu, Belhaire, Eric, Champagnat, Frédéric, Lépine, Thierry, Thales Optronique SA, DOTA, ONERA, Université Paris Saclay (COmUE) [Palaiseau], ONERA-Université Paris Saclay (COmUE), DTIS, ONERA, Université Paris Saclay (COmUE) [Palaiseau], Laboratoire Hubert Curien / Eris, Laboratoire Hubert Curien [Saint Etienne] (LHC), and Université Jean Monnet [Saint-Étienne] (UJM)-Centre National de la Recherche Scientifique (CNRS)-Institut d'Optique Graduate School (IOGS)-Université Jean Monnet [Saint-Étienne] (UJM)-Centre National de la Recherche Scientifique (CNRS)-Institut d'Optique Graduate School (IOGS)

Subjects
[PHYS]Physics [physics], [SPI]Engineering Sciences [physics], CAMERA PLENOPTIQUE, RECOUVREMENT, CHAMP DE LUMIERE, CROSSTALK, LIGHT FIELD, MICROLENS ARRAY, PLENOPTIC CAMERA, MATRICE DE MICROLENTILLES
Abstract

International audience; Crosstalk can affect the performance of a plenoptic camera. In this paper we show that, in the case of a plenoptic 2.0 camera, meeting a F-number matching condition does not provide a crosstalk-free configuration. We then introduce a new set of equations for designing crosstalk-free plenoptic 2.0 cameras.

Published
2016

9. Conception et implémentation d'une caméra plénoptique infrarouge

Author

Cossu, Kevin, Druart, Guillaume, Chambon, Mathieu, Belhaire, Eric, Champagnat, Frédéric, Lépine, Thierry, Thalès Optronique, DOTA, ONERA, Université Paris Saclay (COmUE) [Palaiseau], ONERA-Université Paris Saclay (COmUE), Laboratoire Hubert Curien [Saint Etienne] (LHC), Institut d'Optique Graduate School (IOGS)-Université Jean Monnet [Saint-Étienne] (UJM)-Centre National de la Recherche Scientifique (CNRS), and DTIS, ONERA, Université Paris Saclay (COmUE) [Palaiseau]

Subjects
[PHYS]Physics [physics], [SPI]Engineering Sciences [physics], OPTICAL DESIGN, INFRAROUGE, CHAMP DE LUMIERE, PLENOPTIQUE, ComputingMethodologies_IMAGEPROCESSINGANDCOMPUTERVISION, INFRARED, LIGHTFIELD, MICROLENS ARRAY, CONCEPTION OPTIQUE, PLENOPTIC CAMERA, MATRICE DE MICROLENTILLES
Abstract

International audience; Huge efforts have been made over the past years to miniaturize cameras working in the visible spectrum and to give them new features. Plenoptic cameras for example have emerged as a new way of capturing more than just a single 2D image. These cameras usually include a microlens array positioned between the main lens of the camera and the sensor such that a point in object space is imaged onto multiple pixels. This allows for single snapshot image refocusing or depth estimation. The need for more features in a limited volume is also critical in the military domain. However, defense applications usually require the use of sensors that work in the non-visible spectrum such as cooled infrared sensors. This brings an additional challenge to the design of compact and functionalized cameras. In this paper we explain how we overcame these constraints to design and implement the first cooled infrared plenoptic camera and demonstrate its imaging and distance estimation capabilities.

Published
2016

13. A multi shutter time sensor for multispectral imaging in a 3D Reconstruction embedded sensor

Author

Kolar, Anthony, Graba, Tarik, Pinna, Andrea, Romain, Olivier, Ea, Thomas, Belhaire, Eric, Granado, Bertrand, Laboratoire Traitement et Communication de l'Information (LTCI), Télécom ParisTech-Institut Mines-Télécom [Paris] (IMT)-Centre National de la Recherche Scientifique (CNRS), Département d'électonique, Institut Supérieur d'Electronique de Paris-ISEP, Institut d'électronique fondamentale (IEF), Université Paris-Sud - Paris 11 (UP11)-Centre National de la Recherche Scientifique (CNRS), ASTRE [Cergy-Pontoise], Equipes Traitement de l'Information et Systèmes (ETIS - UMR 8051), Ecole Nationale Supérieure de l'Electronique et de ses Applications (ENSEA)-Centre National de la Recherche Scientifique (CNRS)-CY Cergy Paris Université (CY)-Ecole Nationale Supérieure de l'Electronique et de ses Applications (ENSEA)-Centre National de la Recherche Scientifique (CNRS)-CY Cergy Paris Université (CY), and Granado, Bertrand

Subjects
[INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-AR] Computer Science [cs]/Hardware Architecture [cs.AR], [SPI.TRON] Engineering Sciences [physics]/Electronics, ComputingMilieux_MISCELLANEOUS, [SPI.TRON]Engineering Sciences [physics]/Electronics
Abstract

International audience; no abstract

Published
2007

14. La rétine connexionniste : un nouveau paradigme de rétine artificielle

Author

Pinna, Andrea, Alexandre, Annick, Garda, Patrick, Granado, Bertrand, Belhaire, Eric, ASTRE [Cergy-Pontoise], Equipes Traitement de l'Information et Systèmes (ETIS - UMR 8051), Ecole Nationale Supérieure de l'Electronique et de ses Applications (ENSEA)-Centre National de la Recherche Scientifique (CNRS)-CY Cergy Paris Université (CY)-Ecole Nationale Supérieure de l'Electronique et de ses Applications (ENSEA)-Centre National de la Recherche Scientifique (CNRS)-CY Cergy Paris Université (CY), Institut d'électronique fondamentale (IEF), Université Paris-Sud - Paris 11 (UP11)-Centre National de la Recherche Scientifique (CNRS), and Granado, Bertrand

Subjects
[INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-AR] Computer Science [cs]/Hardware Architecture [cs.AR], [SPI.TRON] Engineering Sciences [physics]/Electronics, ComputingMilieux_MISCELLANEOUS, [SPI.TRON]Engineering Sciences [physics]/Electronics
Abstract

International audience; no abstract

Published
2004

15. La Rétine Connexionniste : Une Rétine artificielle à traitement centralisé

Author

Granado, Bertrand, Pinna, Andrea, Cuenin, Tidiane, Alexandre, Annick, Belhaire, Eric, Garda, Patrick, ASTRE [Cergy-Pontoise], Equipes Traitement de l'Information et Systèmes (ETIS - UMR 8051), Ecole Nationale Supérieure de l'Electronique et de ses Applications (ENSEA)-Centre National de la Recherche Scientifique (CNRS)-CY Cergy Paris Université (CY)-Ecole Nationale Supérieure de l'Electronique et de ses Applications (ENSEA)-Centre National de la Recherche Scientifique (CNRS)-CY Cergy Paris Université (CY), Institut d'électronique fondamentale (IEF), Université Paris-Sud - Paris 11 (UP11)-Centre National de la Recherche Scientifique (CNRS), and Granado, Bertrand

Subjects
[INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-AR] Computer Science [cs]/Hardware Architecture [cs.AR], [SPI.TRON] Engineering Sciences [physics]/Electronics, ComputingMilieux_MISCELLANEOUS, [SPI.TRON]Engineering Sciences [physics]/Electronics
Abstract

International audience; no abstract

Published
2003

16. Contribution to the electronic realization of Artificial Neural Networks : Analog integration of the Boltzmann Machine

Author

Belhaire, Eric, Belhaire, Eric, Institut d'électronique fondamentale (IEF), Université Paris-Sud - Paris 11 (UP11)-Centre National de la Recherche Scientifique (CNRS), Université Paris Sud - Paris XI, and Devos Francis(patrick.garda@upmc.fr)

Subjects
Artificial Neural Network, Cellular automata, Circuits intégrés, Boltzmann machine, optoelectronics, [SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Réseaux de Neurones Formels, [STIC.OTHE]domain_stic/domain_stic.othe, optoélectronique, Machine de Boltzmann, [STIC.OTHE] domain_stic/domain_stic.othe, Modèle Stochastique, Automate Cellulaire, Stochastic model, Analogique, analog design, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, integrated circuits
Abstract

The integration capabilities of MOS technologies has been doubling every eighteen months for twenty years. An attractive approach to exploit this progress has been recently introduced through the invention of “analog cellular circuits” which are built out of the regular interconnexion of thousands identical analog cells. This Thesis is a contribution to the design knowledge of such circuits. It studies those which can be used in pattern recognition applications and which can be modelled by statistical Artificial Neural Networks (ANN). It focuses on the Boltzmann Machine, which is Boolean, stochastic and discrete time ANN model. In Chapter I, the Artificial Neural Network and the algorithms of Synchronous Boltzmann Machine are presented. The Synchronous model is well suited to a parallel implementation. In Chapter II, the State of the art of Boltzmann Machines realizations and the analog techniques used for ANN implementation are presented. In Chapter III, an original architecture of circuits dedicated to multi-layered networks executing Boltzmann Machine is presented. In Chapter IV, the design and simulations of the cells and circuits are described : voltage to current and current to voltage converters, comparator, sigmoidal function. This ANN model requires a stochastic implementation, so two original random generators are presented : the first one is opto-electronic and it takes advantage of the optical speckle properties, the second one is electronic and it uses a chaotic cellular automata. Some measures which have been done on prototype circuits are presented in Chapter V. In summary, future evolution of these techniques towards continuous time implementation and analog neurons state are described., Depuis vingt ans, la capacité d'intégration des technologies MOS double tous les dix-huit mois. Une approche prometteuse pour exploiter cette progression a été introduite récemment par l'invention des “circuits analogiques cellulaires”, qui sont composés de l'assemblage régulier de milliers de cellules analogiques identiques. L'objectif de cette thèse est de contribuer à la conception de ces circuits, en étudiant ceux pour lesquels sont possibles une modélisation statistique à l'aide de Réseaux de Neurones Formels (RNF) et des applications à la reconnaissance des formes. Elle porte plus particulièrement sur la machine de Boltzmann, qui est un modèle de RNF booléen et stochastique, à temps discret. Au chapitre I, je présente les Réseaux de Reurones Formels et les algorithmes de la Machine de Boltzmann Synchrone, qui est un modèle adapté au parallélisme matériel. Au chapitre II, je présente l'état de l'art des réalisations de Machine de Boltzmann et des techniques analogiques utilisées pour les RNF. Au chapitre III, je présente une architecture originale de circuits dédiés aux réseaux multi-couches exécutant la Machine de Boltzmann. Au chapitre IV, je présente la conception et la simulation des cellules et des circuits nécessaires : convertisseurs tension-courant et courant-tension, comparateur, fonction sigmoïde... Ce modèle étant stochastique, je présente aussi deux réalisations originales de générateurs aléatoires : le premier est optoélectronique et tire partie des propriétés du speckle optique, le second est électronique et à base d'automates cellulaires. Le chapitre V est consacré à la description des mesures effectués sur des circuits prototypes de chacune des cellules. En conclusion, je présente les évolutions de ces travaux vers des circuits analogiques à temps continu et à états de neurones continus.

Published
1992

17. Connectionnist Retina : a neural networks system integrated into an electronic retina

Author

Pinna, Andrea, Alexandre, Annick, Belhaire, Eric, Garda, Patrick, Granado, Bertrand, Institut d'électronique fondamentale (IEF), Université Paris-Sud - Paris 11 (UP11)-Centre National de la Recherche Scientifique (CNRS), Laboratoire des Instruments et Systèmes (LIS), and Université Pierre et Marie Curie - Paris 6 (UPMC)

Subjects
[INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], ComputingMilieux_MISCELLANEOUS, [SPI.TRON]Engineering Sciences [physics]/Electronics
Abstract

International audience; no abstract

Published
2002

18. Design of an Integrated Silicon Connectionnist retina

Author

Pinna, Andrea, Alexandre, Annick, Belhaire, Eric, Garda, Patrick, Granado, Bertrand, Institut d'électronique fondamentale (IEF), Université Paris-Sud - Paris 11 (UP11)-Centre National de la Recherche Scientifique (CNRS), Laboratoire des Instruments et Systèmes (LIS), and Université Pierre et Marie Curie - Paris 6 (UPMC)

Subjects
[INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], ComputingMilieux_MISCELLANEOUS, [SPI.TRON]Engineering Sciences [physics]/Electronics
Abstract

International audience; no abstract

Published
2002

19. An embedded neural network system for vision application

Author

Pinna, Andrea, Alexandre, Annick, Belhaire, Eric, Garda, Patrick, Granado, Bertrand, Institut d'électronique fondamentale (IEF), Université Paris-Sud - Paris 11 (UP11)-Centre National de la Recherche Scientifique (CNRS), Laboratoire des Instruments et Systèmes (LIS), and Université Pierre et Marie Curie - Paris 6 (UPMC)

Subjects
[INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], ComputingMilieux_MISCELLANEOUS, [SPI.TRON]Engineering Sciences [physics]/Electronics
Abstract

International audience; no abstract

Published
2002

20. Intégration des réseaux des neurones dans une rétine artificielle

Author

Pinna, Andrea, Alexandre, Annick, Belhaire, Eric, Garda, Patrick, Granado, Bertrand, Institut d'électronique fondamentale (IEF), Université Paris-Sud - Paris 11 (UP11)-Centre National de la Recherche Scientifique (CNRS), Laboratoire des Instruments et Systèmes (LIS), and Université Pierre et Marie Curie - Paris 6 (UPMC)

Subjects
[INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], ComputingMilieux_MISCELLANEOUS, [SPI.TRON]Engineering Sciences [physics]/Electronics
Abstract

International audience; no abstract

Published
2002

21. Conception d'une rétine electronique connexionnistes

Author

Pinna, Andrea, Alexandre, Annick, Belhaire, Eric, Garda, Patrick, Granado, Bertrand, Institut d'électronique fondamentale (IEF), Université Paris-Sud - Paris 11 (UP11)-Centre National de la Recherche Scientifique (CNRS), Laboratoire des Instruments et Systèmes (LIS), Université Pierre et Marie Curie - Paris 6 (UPMC), and Granado, Bertrand

Subjects
[INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-AR] Computer Science [cs]/Hardware Architecture [cs.AR], [SPI.TRON] Engineering Sciences [physics]/Electronics, ComputingMilieux_MISCELLANEOUS, [SPI.TRON]Engineering Sciences [physics]/Electronics
Abstract

International audience; no abstract

Published
2001

28. QWIP development status at Thales

Author

Perrin, Nicolas, primary, Belhaire, Eric, additional, Marquet, Patrice, additional, Besnard, Véronique, additional, Costard, Eric, additional, Nedelcu, Alexandru, additional, Bois, Philippe, additional, Craig, Robert, additional, Parsons, John, additional, Johnston, William, additional, Manissadjian, Alain, additional, and Guinche, Yannick, additional

Published
2008
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31. CMOS/Magnetic Hybrid Architectures

Author

Prenat, Guillaume, primary, El Baraji, Mourad, additional, Guo, Wei, additional, Sousa, Ricardo, additional, Javerliac, Virgile, additional, Nozieres, Jean-Pierre, additional, Zhao, Weisheng, additional, and Belhaire, Eric, additional

Published
2007
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44. Spin Transfer Torque (STT)-MRAM-Based Runtime Reconfiguration FPGA Circuit.

Author

WEISHENG ZHAO, BELHAIRE, ERIC, CHAPPERT, CLAUDE, and MAZOYER, PASCALE

Subjects
FIELD programmable gate arrays, RANDOM access memory, TORQUE, COMPLEMENTARY metal oxide semiconductors, PROGRAMMABLE logic devices, INTEGRATED circuits
Abstract

As the minimum fabrication technology of CMOS transistor shrink down to 90nm or below, the high standby power has become one of the major critical issues for the SRAM-based FPGA circuit due to the increasing leakage currents in the configuration memory. The integration of MRAM in FPGA instead of SRAM is one of the most promising solutions to overcome this issue, because its non-volatility and high write/read speed allow to power down completely the logic blocks in "idle" states in the FPGA circuit. MRAM-based FPGA promises as well as some advanced reconfiguration methods such as runtime reconfiguration and multicontext configuration. However, the conventional MRAM technology based on field-induced magnetic switching (FIMS) writing approach consumes very high power, large circuit surface and produces high disturbance between memory cells. These drawbacks prevent FIMS-MRAM's further development in memory and logic circuit. Spin transfer torque (STT)-based MRAM is then evaluated to address these issues, some design techniques and novel computing architecture for FPGA logic circuits based on STT-MRAM technology are presented in this article. By using STMicroelectronics CMOS 90nm technology and a STT-MTJ spice model, some chip characteristic results as the programming latency and power have been calculated and simulated to demonstrate the expected performance of STT-MRAM based FPGA logic circuits. [ABSTRACT FROM AUTHOR]

Published
2009
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