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87 results on '"Benabdenbi, Mounir"'

11. Test des circuits intégrés numériques - Notions de base et évolutions

Author

Benabdenbi, Mounir, Leveugle, Régis, BEN TITO, Laurence, Architectures and Methods for Resilient Systems (AMfoRS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), and Université Grenoble Alpes (UGA)

Subjects
fault, [INFO.INFO-OH] Computer Science [cs]/Other [cs.OH], defect, PACS 8542, reliability, test, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH]
Abstract

International audience; Test des circuits intégrés numériques - Notions de base et évolutionsLa production de circuits intégrés nécessite un grand nombre d'étapes de fabrication, et cela à des échelles nanométriques. Ces procédés n'étant pas parfaits, le test en fin de fabrication a pour vocation de détecter tous les défauts ayant pu apparaître, avant distribution aux clients. Cet article a pour objectif de présenter les concepts de base, et les méthodes et outils utilisés pour discriminer les circuits avec et sans défauts. Il décrit les types de test, les modèles associés aux défauts physiques et les techniques de génération de vecteurs de test. Il est également fait mention des différentes problématiques rencontrées suite à la miniaturisation continue de la taille des transistors et de leurs impacts sur la qualité de la production sont soulignés.Test of integrated digital circuits - Basic notions and evolutionsProduction of integrated circuits requires a large number of manufacturing steps at nanometric scale. Processes are not perfect so the test at the end of manufacturing aims at detecting all potential defects, before distribution to customers. This article presents the basic concepts, the methods and tools used to discriminate circuits with and without defects. It describes the types of tests, the models associated to physical defects and test vector generation techniques. The problems due to continuous transistor size reduction are also mentioned and their impact on the production quality are underlined.

Published
2021

14. LearnV: A Hardware/Software RISC V Based platform for Research and Education

Author

Ait Said, N., Benabdenbi, Mounir, Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), and BEN TITO, Laurence

Subjects
[SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, PACS 85.42, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, ComputingMilieux_MISCELLANEOUS
Abstract

National audience

Published
2019

15. Teaching Hardware/Software co-design using Rocket Chip

Author

Ait Said, N., Benabdenbi, Mounir, Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), and BEN TITO, Laurence

Subjects
[SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, PACS 85.42, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, ComputingMilieux_MISCELLANEOUS
Abstract

International audience

Published
2019

16. Adjustable Precision Computing using Redundant Arithmetic

Author

Skaf, Ali, Ezzadeen, Mona, Benabdenbi, Mounir, Fesquet, Laurent, Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), and Fesquet, Laurent

Subjects
[SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, ComputingMilieux_MISCELLANEOUS
Abstract

International audience

Published
2019

17. Teaching basic computer architecture, assembly language programming, and operating system design using RISC-V

Author

Andrade Porras, Liliana Lilibeth, Benabdenbi, Mounir, Muller, Olivier, Rousseau, Frédéric, Pétrot, Frédéric, BEN TITO, Laurence, Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019])

Subjects
PACS 85.42, [SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, ComputingMilieux_MISCELLANEOUS
Abstract

National audience

Published
2019

18. mieux comprendre le lien matériel-logiciel en utilisant l’architecture RISC-V et la plateforme Rocket Chip

Author

Ait Said, N., Benabdenbi, Mounir, Villanova Novaes Magalhaes, G., Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), and BEN TITO, Laurence

Subjects
[SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, PACS 85.42, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, ComputingMilieux_MISCELLANEOUS
Abstract

International audience

Published
2018

22. Efficient Fault-Tolerant Adaptive Routing under an unconstrained Set of Node and Link Failures for Many Cores System On Chip

Author

Dimopoulos, M., Gang, Yi, Benabdenbi, Mounir, Anghel, L., Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)

Subjects
network on chip, PACS 8542, fault tolerant circuits, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics
Abstract

International audience; n online fault tolerant routing algorithm for 2DMesh Networks-on-Chip is presented in this work. It combinesan adaptive routing algorithmwith neighbor fault-awareness anda new traffic-balancing metric. To be able to cope with runtimepermanent and temporary failuresthat may result in messagecorruption, message loss or deadlocks, the routing algorithm isenhanced with packet retransmission and a new messagerecovery scheme.Simulation results, for various network sizes, different trafficpatterns, under an unconstrained number of node and link faults,temporary and/or permanent,demonstrate the scalability andefficiency of the proposed algorithmto tolerate multiple failureslikely encountered in deep submicron technologies. As theexperiments have shown, the proposed algorithm maintains highreliability of more than 99.38% for a 2D mesh network of 16x16and in the presence of 384 simultaneous link faults.

Published
2014

23. Cost-efficient Testing of LUT and Intra-cluster Interconnect of a Novel SRAM-based FPGA

Author

Rehman, Saif-Ur, Benabdenbi, Mounir, Anghel, L., Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), and Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)

Subjects
PACS 85.40, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, ComputingMilieux_MISCELLANEOUS
Abstract

International audience

Published
2013

24. An In-Memory Monitoring Database For Self Adaptive MP²SoCs

Author

Faure, Etienne, Marchesan Almeida, Gabriel, Benabdenbi, Mounir, Benoit, Pascal, Clermidy, Fabien, Pêcheux, François, Sassatelli, Gilles, Torres, Lionel, Architecture et Logiciels pour Systèmes Embarqués sur Puce (ALSOC), Laboratoire d'Informatique de Paris 6 (LIP6), Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS)-Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS), Conception et Test de Systèmes MICroélectroniques (SysMIC), Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS), Laboratoire d'Electronique et des Technologies de l'Information (CEA-LETI), and Université Grenoble Alpes (UGA)-Direction de Recherche Technologique (CEA) (DRT (CEA))

Subjects
[SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics
Abstract

International audience; The complexity of MP²SoC architectures to come is such that many issues arise simultaneously, such as multicore programming, system performance, reliability, scalability, etc. The key to solve these issues is self-adaptability: the chips to come have to integrate the required software and hardware means to monitor and self-react to the various kinds of events that are likely to occur during chip's lifetime. The paper describes the design principles of a software based approach used to monitor manycore architectures running multi-threaded functional applications. The approach takes advantage of an in-memory database (as well as appropriate means to store, handle, and retrieve accumulated monitoring data) to achieve the monitoring task as simply as possible. After a presentation of the distributed database (called DRET), a case study is presented, along with performance results that clearly show the interest of the approach.

Published
2010

25. Non-regular 3D mesh Networks-on-Chip

Author

Pasca, V., Anghel, L., Rusu, C., Benabdenbi, Mounir, Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)

Subjects
networks on chip, PACS 85.42, Hardware_INTEGRATEDCIRCUITS, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics
Abstract

International audience; Stacked 3D integration emerged as a key technology for high performance and low power tera-scale computation. It consists in stacking multiple layers of active silicon, possibly in different technologies (i.e. digital, analog, RF, MEMS, etc.), connected with vertical wires called Thru-Silicon-Vias (TSVs). The main benefits of 3D integration rely on the fact that the long intra-die global wires (~mm) are replaced by TSVs with significantly reduced lengths (~ tens of µm). 3D technologies cumulate the intra-die and inter-die defects and parametric faults. Thus, the interconnect yield is significantly reduced. 3D networks-on-chip (NoCs) are the interconnect fabrics on which the Intellectual Property (IP) blocks of 3D systems communicate. In this paper, non-regular D NoCs are proposed. They consist in stacked 2D mesh networks that are connected by inter-die links. The stacked networks are not necessary identical and they reflect the non-uniform distribution of the system's IP blocks. In each layer, only master nodes have ports for inter-die (up and/or down) communication. Non-master nodes communicate with the upper and lower layers through master-up and master-down nodes, respectively. The zone on influence (ZOI) of a master node consists in the routing nodes that use it for inter-die communication.

Published
2010

26. Fault Resilient Intra-die and Inter-die Communication in 3D Integrated Systems

Author

Pasca, V., Anghel, Lorena, Benabdenbi, Mounir, Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), and Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)

Subjects
SoC-communication, PACS 85.42, Hardware_INTEGRATEDCIRCUITS, Hardware_PERFORMANCEANDRELIABILITY, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics
Abstract

International audience; Three-dimensional (3D) integration is an emerging technology that enables Systems-on-Chip (3D SoCs) to achieve higher performance at lower power dissipation. In 3D SoCs, the cumulated effects of the intra-die and inter-die interconnect parametric variations lead to high fault rates. In this paper, a fault resilient scheme for inter-die and intra-die communication in 3D SoCs is proposed. Spare wire insertion and error correction codes ensure resilience against permanent and transient faults, respectively. In very-deep sub-micron (VDSM) technologies, single error correction (SEC) capabilities are not enough to ensure the desired reliability levels. In the proposed link, multi-error correction capabilities are achieved by block / interleaved SEC codes. After the interconnect tests, faulty wires are replaced by functional spares, such that the block/interleaved code-words are transmitted only on functional wires. Increasing the wire noise sensitivity and the inter-wire coupling leads to higher error rate. Thus, the codeword size increases and the link area and power overheads go up to ~30%. For high interconnect defect rates the overheads due the configuration logic lead go up to ~300%.

Published
2010

28. Software-Based Self-Test Strategies for Memory Caches of RISC Processor Cores

Author

Tuna, Matthieu, Garcia, Olivier, Benabdenbi, Mounir, Architecture et Logiciels pour Systèmes Embarqués sur Puce (ALSOC), Laboratoire d'Informatique de Paris 6 (LIP6), Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS)-Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS), and Publications, Lip6

Subjects
[INFO]Computer Science [cs], [INFO] Computer Science [cs], ComputingMilieux_MISCELLANEOUS
Abstract

International audience

Published
2007

29. MP-SoC Architecture for an Obstacle Detection Application in Pre-Crash Situation

Author

Greiner, Alain, Pétrot, Frédéric, Carrier, Mathieu, Benabdenbi, Mounir, Chotin-Avot, Roselyne, Labayrade, Raphaël, Architecture et Logiciels pour Systèmes Embarqués sur Puce (ALSOC), Laboratoire d'Informatique de Paris 6 (LIP6), Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS)-Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), Circuits Intégrés Numériques et Analogiques (CIAN), Laboratoire sur les Interactions Véhicules-Infrastructure-Conducteurs (IFSTTAR/COSYS/LIVIC), Institut Français des Sciences et Technologies des Transports, de l'Aménagement et des Réseaux (IFSTTAR), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS), and Torella, Lucie

Subjects
PACS 8542, [SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, ComputingMilieux_MISCELLANEOUS
Abstract

International audience

Published
2006

30. STESOC: A Software-Based Test-Access-Mechanism Controller

Author

Tuna, Matthieu, Benabdenbi, Mounir, Greiner, Alain, Architecture et Logiciels pour Systèmes Embarqués sur Puce (ALSOC), Laboratoire d'Informatique de Paris 6 (LIP6), Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS)-Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS), and Publications, Lip6

Subjects
[INFO]Computer Science [cs], [INFO] Computer Science [cs]
Abstract

International audience; Software-based test of SoCs consists in testing IP cores using embedded processor cores. Previously proposed solutions are usually ad-hoc. Therefore, this paper presents STESOC, a software-based Test Access Mechanism for SoCs containing standard-wrapped IP cores. Under the control of the embedded microprocessor, a dedicated test-coprocessor tests the remaining components. Using the ITC02 SoC benchmarks a comparison is done between the STESOC architecture and a classical bus-based strategy.

Published
2006

31. Software-Based Self-Test of Register Files in RISC Processor Cores using March Algorithms

Author

Tuna, Matthieu, Benabdenbi, Mounir, Architecture et Logiciels pour Systèmes Embarqués sur Puce (ALSOC), Laboratoire d'Informatique de Paris 6 (LIP6), Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS)-Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS), and Publications, Lip6

Subjects
[INFO]Computer Science [cs], [INFO] Computer Science [cs]
Abstract

International audience; Beside external test and hardware Built-In Self-Test techniques, a non-intrusive low-cost strategy has been developed: Software-Based Self-Test. SBST component-oriented approach for microprocessor allows to reach, with small self-test programs, a high fault coverage. In this context, this paper focuses on the test of the Register File of RISC processor cores. This component has the structure of a small memory. Then, using the appropriate March tests, 100% fault coverage for numerous fault models can be reached. This method was applied to test the Register File of a MIPS microprocessor. Results show that the method allows to obtain small-sized self-test programs while the use of March tests ensures a high test quality.

Published
2006

32. STESI: a new software-based strategy for testing socs containing wrapped IP cores

Author

Tuna, Matthieu, Benabdenbi, Mounir, Greiner, Alain, Architecture et Logiciels pour Systèmes Embarqués sur Puce (ALSOC), Laboratoire d'Informatique de Paris 6 (LIP6), Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS)-Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS), and Publications, Lip6

Subjects
[INFO]Computer Science [cs], [INFO] Computer Science [cs], ComputingMilieux_MISCELLANEOUS
Abstract

International audience

Published
2005

33. STESI: Testing wrapped IP cores using a dedicated Test Processor

Author

Tuna, Matthieu, Benabdenbi, Mounir, Greiner, Alain, Architecture et Logiciels pour Systèmes Embarqués sur Puce (ALSOC), Laboratoire d'Informatique de Paris 6 (LIP6), Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS)-Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS), and Publications, Lip6

Subjects
Hardware_INTEGRATEDCIRCUITS, [INFO]Computer Science [cs], Hardware_PERFORMANCEANDRELIABILITY, [INFO] Computer Science [cs]
Abstract

International audience; This paper presents STESI, a software-based approach for testing SoCs containing wrapped IP cores. In the proposed approach, the test program is no more executed by the traditional ATE but by the SoC itself. The novel feature of the STESI approach is the use of a dedicated test coprocessor embedded on the SoC to test the remaining components. Using the ITC02 SoC benchmarks a comparison is done between the STESI architecture and a classical bus-based strategy.

Published
2005

34. STEPS: experimenting a new software-based strategy for testing SoCs containing P1500-compliant IP cores

Author

Benabdenbi, Mounir, Greiner, Alain, Pêcheux, François, Viaud, Emmanuel, Tuna, Matthieu, Architecture et Logiciels pour Systèmes Embarqués sur Puce (ALSOC), Laboratoire d'Informatique de Paris 6 (LIP6), and Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS)-Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS)

Subjects
Hardware_INTEGRATEDCIRCUITS, [INFO]Computer Science [cs], Hardware_PERFORMANCEANDRELIABILITY
Abstract

International audience; This paper presents STEPS, an innovative software-based approach for testing P1500-compliant SoCs. STEPS is based on the concept that the ATE is not considered as an initiator applying vectors to the SoC test pins but rather as a target, a huge repository of 32-bits test data and control commands. The ATE is connected to the functional SoC external RAM controller interface. The only additional test component in the SoC is a P1500 test processor that converts test data into serial P1500 streams. This paper applies the STEPS methodology to SoCs containing a VCI-compliant interconnect, a microprocessor, P1500-compliant IP cores and an external RAM controller interface. Using the ITC02 SoC benchmarks, a comparison is done between the STEPS architecture and a classical bus-based strategy.

Published
2004

39. A defect-tolerant cluster in a mesh SRAM-based FPGA

Author

Ben Dhia, Arwa, primary, Rehman, Saif Ur, additional, Blanchardon, Adrien, additional, Naviner, Lirida, additional, Benabdenbi, Mounir, additional, Chotin-Avot, Roselyne, additional, Mehrez, Habib, additional, Amouri, Emna, additional, and Marrakchi, Zied, additional

Published
2013
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40. Testing TAPed Cores and Wrapped Cores With The Same Test Access Mechanism

Author

Benabdenbi, Mounir, Maroufi, Walid, Marzouki, Meryem, Architecture des Systèmes intégrés et Micro électronique (ASIM), Laboratoire d'Informatique de Paris 6 (LIP6), and Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS)-Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS)

Subjects
[INFO]Computer Science [cs]
Abstract

International audience; This paper describes a way of testing both wrapped cores and TAPed cores within a System On a Chip (SoC) with the same Test Access Mechanism (TAM). The TAM's architecture, which is dynamically reconfigurable, scalable and flexible, is named CAS-BUS and have a central controller. All the cores can be tested this way in the same session through a modified Boundary Scan Test Access Port.

Published
2001

41. Solving the I/O Bandwidth Problem in System on a Chip Testing

Author

Maroufi, Walid, Benabdenbi, Mounir, Marzouki, Meryem, Architecture des Systèmes intégrés et Micro électronique (ASIM), Laboratoire d'Informatique de Paris 6 (LIP6), and Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS)-Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS)

Subjects
[INFO]Computer Science [cs], Hardware_PERFORMANCEANDRELIABILITY
Abstract

International audience; The first part of this paper describes the control of CAS-BUS, a P1500 compatible Test Access Mechanism (TAM). Boundary scan features are used to allow controlling of the TAM and the P1500 wrappers. The final architecture characteristics are its flexibility, scalability and reconfigurability. It also allows trade-off to optimize test time and area overhead. The second part deals with a test pin expansion method in order to solve the bandwidth problem. The solution we propose is based on a new compression/decompression mechanism which avoid TAM performances degradation.

Published
2000

42. Controlling the CAS-BUS TAM with IEEE 1149.1 TAP: A Solution for Systems-On-a-Chip Testing

Author

Maroufi, Walid, Benabdenbi, Mounir, Marzouki, Meryem, Architecture des Systèmes intégrés et Micro électronique (ASIM), Laboratoire d'Informatique de Paris 6 (LIP6), Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS)-Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS), and Publications, Lip6

Subjects
[INFO]Computer Science [cs], [INFO] Computer Science [cs], ComputingMilieux_MISCELLANEOUS
Abstract

International audience

Published
2000

43. CAS-BUS: A Scalable and Reconfigurable Test Access Mechanism for Systems on a Chip

Author

Benabdenbi, Mounir, Maroufi, Walid, Marzouki, Meryem, Architecture des Systèmes intégrés et Micro électronique (ASIM), Laboratoire d'Informatique de Paris 6 (LIP6), and Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS)-Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS)

Subjects
Hardware_MEMORYSTRUCTURES, ComputingMethodologies_SYMBOLICANDALGEBRAICMANIPULATION, [INFO]Computer Science [cs], Hardware_PERFORMANCEANDRELIABILITY
Abstract

International audience; This paper describes CAS-BUS, a P1500 compatible test access mechanism for systems on a chip. The TAM architecture is made up of a core access switch (CAS) and a test bus. The TAM characteristics are its flexibility, scalability and reconfigurability. A CAS generator has been developed, and some results are provided in the paper.

Published
2000

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