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International audience; The demand for high resolution CMOS image sensors (CIS) is rising. Analog-to-digital converters (ADC) represent one of the major bottleneck of CIS. One of the candidates to overcome the existing limits is the column-parallel ADC. Column-parallel extended counting ADCs (EC-ADC) are able to reach high resolution thanks to their two-step conversion. However the EC-ADC area increases due to the two-step design. A solution is to use the same hardware twice to perform both steps. This paper proposes a 14-b, 100 kHz Nyquist frequency, two-step incremental Σ∆ (IΣ∆) analog-to-digital converter suitable for column-parallel CIS. Several architectures with different modulator order are compared to determine the most promising one. The proposed architecture, compared to a one-step second order modulator, reduces the total oversampling ratio (OSR) from 150 to 60 to reach a resolution of 14-b. The operational transconductance amplifiers (OTA) is the most critical part in our ADCs. Its required DC-gain is around 80 dB for a 120 MHz gain-bandwidth product (GBW). The ideal DNL and INL of our two-step IΣ∆ ADC are respectively +0.55/-0.6 LSB and +0.5/-0.5 LSB. This work achieves a SNDR of 89 dB when a full scale sinusoid of 100 kHz is applied. Index Terms—ADC, incremental, sigma-delta (Σ∆), two-step, CMOS Image Sensor, column-parallel ADC, second-order Σ∆

International audience; Today's applications such as broadband satellite receivers, cable TVs, and software-defined radios require highly efficient ADCs with high sampling rates and high resolutions. A time-interleaved ADC (TIADC) is a popular architecture used to achieve this goal. However, this structure suffers from mismatches between the sub-converters, which cause errors on the output signal, and more significantly, decrease the SFDR. These mismatches can be a severe limitation in applications such as satellite reception, where both narrowband and wideband signals are used. This paper introduces digital derivative-based estimation of timing mismatches. Gain, offset and skew mismatch calibrations are performed entirely in the digital domain through equalization.

National audience; This paper reports on a theoretical study of the efficiency of a switched capacitor converter for autonomous sensors. The sensor is composed of an energy harvester (Solar cell), the electronic system (micro-controller, radio, temperature sensor, MEMS. . . ) and a battery. Based on our theory, we calculate this efficiency with respect to: the switching frequency, the capacitance values and the battery voltage. We present this using 3-D graphs. This theory is based on Ultra-Low-Power Embedded systems such as wireless sensors with photovoltaic harvesters operating in low-light conditions. In this case, the harvested energy from PV do not exceed a few tens of micro-watts, which forbids the use of "power-hungry" coil-based power converters. On the contrary, using switched capacitors converter is a better alternative for this kind of application. We here present a theoretical framework deriving the maximum efficiency achieved by a switched capacitor converter with respect to: the switching frequency, the capacitance value and the battery voltage.

The invention relates on a sigma delta digital to analog converter, digitally sequenced by a clock, comprising a main line and a feedback line, the main line comprising: an input port, a linear filter G(z) and a multibit quantifier, a digital to analog converter, an output port, and the feedback line comprising a correcting memory table, able to process a correcting signal, and an adder able to subtract said correcting signal from an input signal, wherein the correcting memory table time cycle is k times greater than the clock time cycle.

Most of the recent design methodologies of continuous-time sigma-delta modulators use piezo-electric resonators as loop filters. Compared with classical resonators (Gm-c,Gm-LC and etc), piezo-electric resonators have the advantage of high quality factor and accurate resonance frequency. However, they suffer from anti-resonance frequency and impedance adaptation issues with connected electronic circuits. Therefore, their performance is in practice deteriorated. Compatible electronic control circuit is required to achieve expected performance. In this study, the specifications of the electronic control circuit are studied and this circuit is designed in AMS Bi-CMOS 0.35μm technology. the simulations are done at layout-level.

International audience; Frequency-Band-Decomposition (FBD) is a good candidate to increase the bandwidths of ADC converters based on sigma-delta modulators. Each modulator processes a part of the input signal band and is followed by a digital filter. In the case of large mismatches in the analog modulators, a new solution, called Extended Frequency-Band-Decomposition (EFBD) can be used. This solution allows for, for example, a four percent error in the central frequencies without significant degradation in the performance when the digital processing part is appeared to the analog modulators. A calibration of the digital part is thus required to reach these theoretical performance. This paper will focus on a self-calibration algorithm for an EFBD. The algorithm helps minimize the quantization noise of the EFBD.

An analysis and synthesis method for continuoustime (CT) band-pass delta-sigma modulators, applicable in parallel converters is presented in this paper. This method makes the design of band-pass delta-sigma modulators possible in a wide range of central frequencies and high DAC+ADC delays. This method is also applicable for narrow-band deltasigma converters in order to improve their performances.

International audience; A methodology for the simulation of bandpass continuous time sigma-delta (SD) modulators is presented in this paper. This method permits the simulation of SD modulators employing continuous-time filters using a fixed-step algorithm. The method is based on the discretization of a continuous-time model and the use of a discrete simulator, which is more efficient than an analog simulator. This transformation is exact in term of Noise Transfer Function and asymptotically exact in term of Signal Transfer Function (the Signal Transfer Function of the model rapidly tends to the continuous time model transfer function when the number of steps increases).

International audience; A methodology for the simulation of continuous time sigma-delta (ΣΔ) converters is presented in this paper. This method permits the simulation of ΣΔ modulators employing continuous-time filters using a fixed-step algorithm. The analysis method is based on the discretization of a continuous-time model and using a discrete simulator, which is more efficient than an analog simulator. In our analysis approach, each samplingperiod is divided into a fixed number of steps. This transformation is exact in term of Noise Transfer Function and asymptotically exact in term of Signal Transfer Function (the Signal Transfer Function of the model rapidly tends to the continuous time model transfer function when the number of steps increases). Moreover, the ideal step-size can be estimated from the bandwidth of the input signal.

National audience; Cet article présente un convertisseur analogique-numérique possédant deux modes de fonctionnement. Le premier mode se caractérise par une très faible consommation, associée à une faible résolution (9 bits). Dans le second mode, la résolution est accrue de 6 bits en théorie ; en contrepartie, la consommation augmente. En mode « faible consommation », le système est un convertisseur sigma-delta passif c'est-à-dire dont le modulateur utilise un filtre passe-bas passif, le seul élément actif étant le comparateur. En mode « haute résolution », le modulateur passif est positionné dans une boucle comprenant notamment un filtre passe-bas actif. Le principe de cette topologie bi-modes a été validé par des simulations au niveau fonctionnel et par le test d'un circuit prototype réalisé en technologie CMOS 0.350m.

International audience; Resolution of a multibit delta-sigma modulator (DSM) is limited by its internal digital-to-analog converter (DAC) nonlinearity that is usually caused by circuit mismatch errors while realizing. Recently, some dynamic element matching (DEM) methods were proposed for reducing mismatch errors. Two main difficulties of different dynamic element matching (DEM) techniques relate to instability and complexity of their algorithms. This paper provides a general method to simplify and to improve stability of high order dynamic element matching algorithms. It is shown that the proposed modifications can reduce necessary hardware for any order of sorting DEM algorithms and improve stability of the high order tree-structured DEM, without scarifying a considerable part of their ideal mismatchshaping function. Simulations are presented for different 6th and 4th-order bandpass mismatch-shaping circuit, moved inside the feedback loop of a 6th-order bandpass delta-sigma modulator. However, it can also be used in lowpass DSM.

International audience; This paper presents a new method for digitizing wideband signals. It is based on the use of parallel analog delta sigma modulators, where each modulator converts a part of the input signal band. A major benefit of the architecture is that it widens the conversion band of the input signal and increases its dynamic range. Two solutions are proposed to reconstruct the signal: the first one uses bandpass filters without demodulation and the second demodulates the signal of each modulator, and then processes it in a lowpass filter. This paper focuses essentially on the digital part of the system and the overall performances are compared by using simulation results.