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This article presents a delta sigma modulator (DSM) analog to digital (ADC) that uses ring amplifiers as integrators to relax speed and efficiency bottlenecks in discrete-time (DT) oversampled ADCs. Its multi-bit quantizer is based on split source (SS) comparators, adding flexibility and power efficiency. The complete oversampling ADC is designed as a 3rd-order cascade of integrator with feed forward (CIFF) with a 4-bit quantizer, and it achieves a peak signal-to-noise and distortion ratio (SNDR) of 67 dB and DR of 70.0 dB with 47.5-MHz bandwidth when clocked at 950 MHz. This is the highest bandwidth reported to date among single-channel DT DSM ADCs and demonstrates a viable alternative to continuous-time (CT) DSM ADCs for wideband oversampling applications. With a power consumption of 4.7 mW from a 1-V supply, figure of merit (FoM) Schreier and Walden are 167.0 dB and 27.0 fJ/c.s, respectively, demonstrating efficient DT delta-sigma conversion with high bandwidth.

A $4\times $ interleaved pipelined ADC for direct-RF sampling applications is presented. It leverages the performance advantages of ring amplifiers to unlock greater architectural freedom. The first pipeline stage MDAC with a “passive-hold” mode eliminates the sub-ADC sampling path and associated problems. A high-speed ringamp topology employs digital bias control, robust common-mode feedback (CMFB), and an elegant self-resetting behavior. An asynchronous, event-driven timing control system improves several aspects of performance and enables fully dynamic power consumption and modular design re-use. A general technique is presented whereby the signal-to-distortion ratio (SDR) of any amplifier in the system can be measured in the background with an analog hardware overhead of only one comparator. In this amplifier-intensive architecture utilizing 36 ringamps, the 4-GS/s ADC fabricated in 16-nm CMOS achieves 62-dB SNDR and 75-dB SFDR at Nyquist, consumes 75 mW (including input buffer), and has a Walden figure of merit (FoM) of 18 fJ/conversion-step and a Schreier FoM of 166 dB, advancing the state of the art in direct-RF sampling ADCs by roughly an order of magnitude.

An asynchronous event-driven approach to clocking and timing control is explored in the context of pipelined ADCs. It is shown how a conventional global clock tree can be replaced by localized control units coordinated through inter-stage communication protocols. The approach is found to yield many compelling advantages in terms of power efficiency, speed, robustness, and reconfigurability. It is shown how these benefits are particularly well leveraged when used in combination with dynamic-power residue amplifiers such as ring amplifiers. Several challenges also arise: re-synchronization of the digital outputs, mitigation of possible deadlock scenarios, and robust timing control configuration. Solutions to these problems are presented. Two single-channel 11-bit 1.5-bit/stage pipelined ADC designs are fabricated in a 16nm CMOS technology, each with a different implementation approach to the asynchronous control units. The trade-offs of both approaches are considered. At 1 GS/s the fastest prototype achieves 59.5 dB SNDR and 75.9 dB SFDR at Nyquist, consuming 10.9 mW including reference regulator. Due to fully-dynamic operation, it maintains a near-constant Walden Figure of Merit (FoM) of 14 fJ/conversion-step from 1 MS/s to 1 GS/s.

This article presents a fully dynamic ringamp-based pipelined ADC with integrated reference buffer that operates from 1-MS/s to 1-GS/s and maintains a Walden Figure-of-Merit (FoM) of 14 fJ/conversion-step across this range. A “split-reference” regulation technique is introduced, which provides multiple buffered replicas with varying accuracies and output impedances to the core ADC circuitry, relaxing overall buffer design requirements and improving efficiency. The regulator blocks are implemented with fully dynamic discrete-time loops. Furthermore, a technique for background reconstruction of residue amplifier settling behavior is also described. The “scope-on-chip” captures high-resolution transient waveforms using a 1-bit stochastic ADC. It is shown how these waveform data can be used for optimization of ringamp biasing and PVT tracking. The ADC is fabricated in a 16-nm CMOS technology and at 1 GS/s with a Nyquist input achieves 59.5-dB SNDR, 75.9-dB SFDR, and 10.9-mW total power consumption with only 8% consumed by the reference regulation.

This work presents a discrete-time (DT) delta sigma modulator (DSM) ADC that uses ring amplifiers to relax critical speed and efficiency bottlenecks. The DSM is designed as a 3 rd -order Cascade of Integrator with Feed Forward (CIFF) with a 4-bit quantizer, and it achieves a peak SNDR of 67dB and DR of 70.0dB with 47.5MHz bandwidth when clocked at 950MHz. This is the highest bandwidth reported to-date among single-channel DT DSM ADCs and demonstrates a viable alternative to continuous-time (CT) DSM ADCs for wideband oversampling applications. With a power consumption of 4.7mW from a 1V supply, FOMs and FOMw are 167.0dB and 27.0fJ/c.s. respectively, demonstrating efficient DT delta-sigma conversion with high bandwidth.

We present a single-channel fully-dynamic pipelined SAR ADC that leverages a novel quantizer and narrowband dither injection to achieve fast and comprehensive background calibration of DAC mismatch, interstage gain, and ring amplifier (ringamp) bias optimality. The ADC also includes an on-chip wide-range, fully-dynamic reference regulation system. Consuming 3.3 mW at 500 MS/s, it achieves 10.0 ENOB and 75.5 dB SFDR, yielding a Walden FoM of 6.2 fJ/c.s.

This paper presents an 11 bit fully dynamic pipelined ADC with an integrated reference buffer that consumes only 8% of total power. It operates from 1MS/s to 1GS/s and maintains 59.5dB SNDR and 14fJ/conv-step FoM W across this range. Furthermore, a small circuit is introduced that provides background reconstruction of amplifier settling behavior.

A two-time interleaved pipelined SAR ADC in 16-nm CMOS achieving 11.2-bit ENOB at 300 MS/s is presented. To cancel the signal-dependent voltage ripple on the reference node due to DAC switching, it employs a stabilization scheme based on the use of auxiliary DACs. The charge drawn from the reference becomes signal-independent, greatly reducing the requirements for the reference decoupling capacitance and/or buffers. The technique improves the linearity to levels better than 76-dB harmonic distortion. Power consumption is only 3.6 mW resulting in peak FoMs of 175.5 dB and 5.1 fJ/conv.step.

At the upper end of achievable ADC operating speeds, clocking becomes a critical performance limiter. In “deep” pipelined ADCs that contain many stages, the clock tree constitutes a highly distributed network, with parasitics and mismatch creating skew between the different branches. Sufficient margin must be included in the timing generation such that all non-overlap and causal relationships are maintained. This leads to a difficult set of design tradeoffs in terms of power, speed, jitter, and reliability. Meanwhile, although residue amplifiers have traditionally dominated the power budget in deep pipelines, recent advances such as ring amplification have improved achievable efficiencies to the point that clocking is now the primary consumer in some cases [1, 2].

An electrical-balance duplexer achieving the state-of-the-art linearity and insertion loss (IL) performance is presented, enabled by a partially depleted RF silicon-on-insulator CMOS technology. A single-ended configuration avoids the common-mode isolation problem suffered by topologies with a differential low-noise amplifier. Highly linear switched capacitors allow for impedance balancing to antennas with

Ring amplification has recently been shown capable of simultaneously achieving high linearity and high bandwidth (BW) in low-voltage, deep nanoscale CMOS processes, while retaining good power efficiency. In these processes, the low but very flat open-loop (OL) gain versus output voltage characteristic of the ring amplifier can be exploited, together with its high BW, to overcome the low intrinsic gain limitations that otherwise mandate the use of power-consuming analog circuits and complex digital calibration. Within this context, this paper introduces the techniques of dead-zone degeneration (DZD) and second-stage bias enhancement to further extend the linearity and speed limits of the ring amplifier, respectively. These techniques are applied to a 12-b, 1-GS/s, single-channel pipelined ADC implemented in a 28-nm planar CMOS process, which achieves 56.6-dB SNDR and 73.1-dB SFDR while consuming 24.8 mW from a single 0.9-V supply, resulting in Schreier and Walden figure-of-merit (FoM) values of 159.6 dB and 45 fJ/conv.-step, respectively.

Achieving high linearity and bandwidth with good power efficiency makes the design of ADCs in deep nanoscale CMOS processes very challenging, as the constraints of low-voltage operation and limited intrinsic gain often dictate the use of power-consuming analog circuits and intensive digital calibration. This paper addresses these problems by introducing a pipelined ADC that exploits the low but very constant open-loop gain versus output voltage characteristic of the ring amplifier (ringamp) to achieve both high speed and linearity in low-voltage nanoscale CMOS designs. A tunable ringamp biasing scheme using an anti-parallel arrangement of CMOS transistors and an active ringamp-based common-mode feedback are also introduced. A single-channel prototype ADC is implemented in a standard 28-nm CMOS process, achieving 58.7-dB SNDR and 72.4-dB SFDR at 600 MS/s while consuming 14.5 mW from a single 0.9-V supply, resulting in Walden and Schreier figure-of-merit (FoM) values of 34.4 fJ/conv.-step and 161.9 dB, respectively.

The design of power-efficient ADCs able to achieve both high linearity and bandwidth in deep nanoscale CMOS processes becomes very challenging as the constraints of low-voltage operation and limited intrinsic gain often mandate the use of power-consuming analog circuits and digital calibration. This work introduces a pipelined ADC that leverages the low but very flat open-loop gain vs. output swing characteristic of the ring amplifier (ringamp) to address these problems. A 12-bit, 1Gsps, single-channel prototype is implemented in a 28nm planar CMOS process achieving 56.6dB SNDR and 73.1dB SFDR. Consuming 24.8mW from a single 0.9V supply, it achieves Schreier and Walden FoMs of 159.6dB and 45fJ/conv.-step, respectively.

This paper describes a fractional-N subsampling PLL in 28 nm CMOS. Fractional phase lock is made possible with almost no penalty in phase noise performance thanks to the use of a 10 bit, 0.55 ps/LSB digital-to-time converter (DTC) circuit operating on the sampling clock. The performance limitations of a practical DTC implementation are considered, and techniques for minimizing these limitations are presented. For example, background calibration guarantees appropriate DTC gain, reducing spurs. Operating at 10 GHz the system achieves −38 dBc of integrated phase noise (280 fs RMS jitter) when a worst case fractional spur of −43 dBc is present. In-band phase noise is at the level of −104 dBc/Hz. The class-B VCO can be tuned from 9.2 GHz to 12.7 GHz (32%). The total power consumption of the synthesizer, including the VCO, is 13 mW from 0.9 V and 1.8 V supplies.

A pipelined ADC is presented that exploits the low but very constant (over output swing) open-loop gain characteristic of the ring amplifier (ringamp) to achieve high SFDR in low-voltage nanoscale CMOS designs. A dynamic ringamp biasing scheme using CMOS resistors and an active ringamp-based common-mode feedback (CMFB) are also introduced. The implemented prototype achieves 56.3dB SNDR and 69.2dB SFDR at 600Msps, consuming 14.2mW from a 0.9V supply, resulting in a Figure-of-Merit (FoM) of 44.3fJ/conv.-step.

We present a 300 MSps 2 times interleaved pipelined SAR ADC in 16nm digital CMOS. It implements a new scheme to cancel reference voltage ripple due to DAC switching, greatly reducing requirements for decoupling capacitance and/or reference buffering, and achieves better than 76dB harmonic distortion. At 300 MSps, the peak ENOB is 11.2 bit with a power consumption of 3.6mW.

A comparator circuit with a built-in programmable threshold is proposed. The threshold is embedded by providing different initial source voltages to each of the input transistors. This source-voltage shifting is done by means of a tunable capacitance, which can synthesise a very wide range of initial voltages, even voltages beyond the supply. This results in a power-efficient comparator structure with a very wide programmable tuning range and low decision delay. The inherently small integrating capacitance of the structure allows for high speed operation even when using small device sizes, minimising input capacitance and maximising efficiency. A practical transistor-level implementation is simulated in a standard 16 nm CMOS technology on a 0.8 V supply, with a tuning range of at least ± 568 mV.

It is demonstrated in this paper that it is possible to synthesize a stochastic flash ADC entirely from Verilog code and a standard digital library. An analog comparator is introduced that is constructed from two cross-coupled 3-input digital NAND gates, and can be described in Verilog. The synthesized comparators have random, Gaussian offsets that are used as virtual voltage references to make a flash ADC. A piecewise-linear inverse Gaussian CDF function is used to correct the nonlinearity introduced by the Gaussian offset distribution. The prototype IC is fabricated in 90 nm CMOS and implements a 2047-comparator version of the proposed architecture. All components including the comparators, the ones adder, and the peicewise inverse Gaussian function are all implemented in Verilog. Conventional digital synthesis and place-and-route is then used to generate the physical layout, making this the first fully synthesized ADC. SNDR of 35.9 dB (without calibration) is achieved at 210 MSPS from the Verilog synthesized design.

We present an analog subsampling PLL based on a digital-to-time converter (DTC), which operates with almost no performance gap (176/198 fs RMS jitter) between the integer and the worst case fractional operation, achieving −246.6 dB FOM in the worst case fractional mode. The PLL is capable of two-point, 10 Mbit/s GMSK modulation with −40.5 dB EVM around a 10.24 GHz fractional carrier. The analog nonidealities—DTC gain, DTC nonlinearity, modulating VCO bank gain, and nonlinearity—are calibrated in the background while the system operates normally. This results in ~15 dB fractional spur improvement (from −41 dBc to −56.5 dBc) during synthesis and ~15 dB EVM improvement (from −25 dB to −40.5 dB) during modulation. The paper provides an overview of the mechanisms that contribute to performance degradation in DTC-based PLL/phase modulators and presents ways to mitigate them. We demonstrate state-of-the-art performance in nanoscale CMOS for fractional-N synthesis and phase modulation.

This paper proposes the concept of electrical balance filters to enable integrated, tunable RF filters, where a pass- and stopband are designed by the change in electrical-balance across frequency. These filters can be constructed using low Q integrated LC resonators. The stopband frequency is the frequency where two on chip balance networks are tuned to be equal in impedance or ‘balanced’, while the passband frequency is the frequency where the balance condition is disturbed as much as possible for low insertion loss. A 1.5mm2 electrical balance low-pass filter prototype is implemented in 0.18μm SOI CMOS. It has 60dB, >33MHz stopband tunable from 1.75 to 3.7 GHz.

In this paper the fundamental concept of ring amplification is introduced and explored. Ring amplifiers enable efficient amplification in scaled environments, and possess the benefits of efficient slew-based charging, rapid stabilization, compression-immunity (inherent rail-to-rail output swing), and performance that scales with process technology. A basic operational theory is established, and the core benefits of this technique are identified. Measured results from two separate ring amplifier based pipelined ADCs are presented. The first prototype IC, a simple 10.5-bit, 61.5 dB SNDR pipelined ADC which uses only ring amplifiers, is used to demonstrate the core benefits. The second fabricated IC presented is a high-resolution pipelined ADC which employs the technique of Split-CLS to perform efficient, accurate amplification aided by ring amplifiers. The 15-bit ADC is implemented in a 0.18 μm CMOS technology and achieves 76.8 dB SNDR and 95.4 dB SFDR at 20 Msps while consuming 5.1 mW, achieving a FoM of 45 fJ/conversion-step.

A low-power synthesizable analog-to-digital converter (ADC) is presented. By cascading many digital-like domino-logic cells whose propagation delay is influenced by an analog input voltage, a digital value is obtained at the end of the allowed ripple period by determining the number of cells that the ripple passed through. The sample-and-hold is simply a bootstrapped switch into a small sampling capacitor. As each domino-logic cell passes the ripple, charge is kicked back onto the input capacitor, which creates a significant second harmonic. Distortion caused by even harmonics is canceled by implementing a pseudodifferential structure. A test chip is fabricated in 0.18-μm CMOS. The test chip achieves over 5.4-bit effective number of bits up to 50 MS/s with a 1.3-V supply. With a sampling frequency of 50 MS/s and a 24-MHz input, a 34.2-dB signal-to-noise-plus distortion ratio is achieved while consuming 433 μW and occupying only 0.094 mm2.

Building on the technique of correlated level shifting (CLS), Split-CLS is introduced as a viable way to enable the design of high performance, high resolution A/D converters in deep submicron CMOS processes. One possible implementation of Split-CLS is presented, which achieves very high effective gain, and combines the fast, high efficiency charging of a zero-crossing based circuit (ZCBC) with the high-accuracy, low power settling of a double-cascode telescopic opamp. A dynamic zero-crossing detector (ZCD) conserves power in the ZCBC by only creating high bandwidth in the ZCD near the zero-crossing instant. Measured results are presented from a pipelined A/D converter fabricated in 0.18 m CMOS. Using the Split-CLS structure, an opamp with 300 mV output swing is used to produce a pipeline stage output swing of 1.4 V. The proof-of-concept test chip achieves 68.3 dB SNDR (11.1b ENOB) and 76.3dB SFDR while sampling at 20 MHz, and consumes 17.2 mW at 1.8 V supply.

A stochastic flash analog-to-digital converter (ADC) is presented. A standard flash uses a resistor string to set individual comparator trip points. A stochastic flash ADC uses random comparator offset to set the trip points. Since the comparators are no longer sized for small offset, they can be shrunk down into digital cells. Using comparators that are implemented as digital cells produces a large variation of comparator offset. Typically, this is considered a disadvantage, but in our case, this large standard deviation of offset is used to set the input signal range. By designing an ADC that is made up entirely of digital cells, it is a natural candidate for a synthesizable ADC. Comparator trip points follow the nonlinear transfer function described by a Gaussian cumulative distribution function, and a technique is presented that reduces this nonlinearity by changing the overall transfer function of the stochastic flash ADC. A test chip is fabricated in 0.18- CMOS to demonstrate the concept.

The two-point injection scheme has proven to be an effective technique for overcoming the problem of PLL bandwidth limitations during wideband polar phase modulation [1]. The quality of the phase-modulated signal, typically expressed in terms of error-vector magnitude (EVM), still remains limited by the PLL phase-noise, gain mismatch between the two injection paths and linearity of the digital-to-modulated phase conversion. We present a phase modulator that makes use of an analog, fractional-N, digital-to-time-converter (DTC)-based subsampling PLL that achieves −37.4dB EVM around a 10.24GHz fractional carrier during 10Mb/s GMSK modulation. The subsampling PLL architecture uses no power-consuming divider and allows wide PLL bandwidth (because of its high phase-error detection gain) for optimal VCO noise suppression. The VCO has a secondary, digitally controlled capacitor bank (modulating DAC) used during two-point modulation. The gain errors and nonlinearities in the digital-to-modulated phase conversion are automatically background-calibrated in both injection points: in the phase-error detection path (where nonlinearity is dominated by the DTC INL) and in the VCO modulating capacitor bank (where nonlinearity is dominated by capacitor mismatch and nonlinear capacitance-to-frequency conversion).

An electrical-balance duplexer (EBD) is a tunable RF front-end concept that seeks to address several key challenges of 4G and 5G mobile systems [1]. The basic principle is shown in Fig. 20.8.1. Duplexer isolation is achieved when the signals in paths 1 and 2 cancel and prevent the TX signal from appearing at the RX port. This cancellation is achieved by “balancing” the antenna impedance ZANT with an on-chip tunable impedance ZBAL.

In-band full-duplex is a promising air interface technique to tackle several of the key challenges of next generation (5G) mobile networks. Simultaneous transmission and reception in the same frequency band increases the throughput and spectral efficiency, and reduces the air interface delay. Its implementation in 5G systems, however, restrains the full-duplex transceiver design requirements. Two analog integrated circuit solutions are presented and evaluated in the frame of 5G applications. The first design is a self-interference cancelling front-end implemented in 65nm CMOS, and the second design is an electrical-balance duplexer implemented in 0.18µm RF SOI CMOS. Both designs are attractive in the context of 5G; they allow dense integration, are configurable to support alternative and legacy standards, are compatible with conventional antenna(s), and they provide an attractive full-duplex performance for wireless communications.

The electrical-balance (EB) duplexer concept explored in [1-4] suggests a possible integrated multiband alternative to conventional fixed-frequency surface-acoustic-wave (SAW) duplexers. The basic principle of the EB duplexer is to balance the impedances seen at the ports of a hybrid transformer to suppress signal transfer from the TX to the RX through signal cancellation (Fig. 2.2.1). While the potential payoff is tantalizing, several challenges must still be solved before EB duplexers can become commercially viable. Specifically, the duplexer must provide high isolation and linearity in both the TX and RX bands across wide bandwidth (BW), with low insertion loss (IL), all in the presence of a real antenna whose impedance is constantly varying due to real-world user interaction. In this paper, we present a duplexer that significantly advances the state-of-the-art for two of these critical challenges: linearity and insertion loss.

A wide tuning range class-B VCO in 28nm CMOS targeted for software defined radio applications demonstrates a technique for minimizing device stress while simultaneously optimizing off-state Q in digitally switched tank capacitor cells. The proposed digital varactor structure can be implemented using only capacitors and NMOS transistors, resulting in a very compact layout. The VCO operates between 9.1 – 12.7 GHz, achieving a tuning range of 32% and phase noise of −163.2 dBc/Hz at 20 MHz offset referred to a 915 MHz carrier while consuming 9.5 mW for a FoM of −187 dBc/Hz.

Ring amplification is a technique for performing efficient amplification in nanoscale CMOS technologies. By using a cascade of dynamically stabilized inverter stages to perform accurate amplification, ring amplifiers are able to leverage the key benefits of technology scaling, resulting in excellent efficiency and performance. A generalized view of basic small-signal theory is first presented, followed by a deeper discussion of the time-domain operation of a ringamp in the context of a specific ringamp structure. We conclude with a survey of existing ringamp implementations and techniques reported in literature.

This paper describes a fractional-N subsampling PLL in 28nm CMOS. Fractional lock is achieved by using a 10bit digital-to-time converter (DTC) that generates a delayed sampling clock with minimal impact on PLL performance. Background calibration guarantees appropriate DTC gain, reducing spurs. The system achieves -38 dBc of integrated phase noise (280fs RMS jitter) at 10GHz when a worst-case fractional spur of -43 dBc is present. In-band phase noise is at the level of -104 dBc/Hz. The class-B VCO used can be tuned from 9.2 GHz to 12.7 GHz (32%). The total power consumption of the synthesizer, including the VCO, is 13 mW from 0.9V and 1.8V supplies.

This paper presents a unified classification model for gain enhancement techniques used in the design of high performance amplifiers. A parallel gain enhancement technique is proposed for switched capacitor circuits which combine the best features of the existing gain enhancement techniques found in continuous-time and discrete-time amplifiers. This technique utilizes two dependent closed loop amplifiers to enhance the open loop DC gain of the main amplifier. This replicated parallel gain enhancement (RPGE) technique enables a very high DC gain amplifier with an improved harmonic distortion performance. A proof of concept pipeline ADC in a 0.18 um CMOS process using RPGE technique achieves 75 dB SNDR, 91 dB SFDR, -87 dB THD at 20 MS/s. The measured 13 bit DNL and INL is +0.75/-0.36 and +0.88/-0.92 LSB respectively. The ADC operates from a supply voltage of 1.3 V, consumes 5.9 mW, occupies 3.06 mm2 and achieves a figure of merit of 65 fJ/CS.

A ring amplifier based pipelined ADC is presented that uses simple cells constructed from small inverters and capacitors to perform amplification. The basic ring amplifier structure is characterized and demonstrated to be highly scalable, power efficient, and compression-immune (inherent rail-to-rail output swing). The prototype 10.5-bit ADC, fabricated in 0.18µm CMOS technology, achieves 61.5dB SNDR at a 30MHz sampling rate and consumes 2.6mW, resulting in a FoM of 90fJ/conversion-step.

The relation between opamp noise and the size of the level shifting capacitor in correlated level-shifting (CLS) architectures is explored. Analysis is performed for a Split-CLS switched capacitor amplification circuit, and many of the conclusions in this paper are applicable to more general CLS architectures as well. A theoretical model for noise is developed and shown to be in good agreement with simulation. It is found that for practical design values, the size of the level-shifting capacitor only weakly influences noise performance.

An optimized memory structure, Binary Access Memory (BAM), is presented for successive approximation applications that employ an error correction lookup table. Unlike true random-access memory, the probability of different codes occurring in a binary successive approximation access pattern is not uniformly distributed. BAM exploits this fact in several ways to reduce the number of sub-block switches, the average and worst-case access latency, and power consumption compared to a conventional SRAM lookup table. A simple technique for using BAM in an asynchronous successive approximation design is also presented.

The equation for calculating ENOB from SNDR of a sine-wave test is only accurate when noise is uncorrelated to the input. In this paper, the equation for calculating ENOB from SNDR is derived for an ideal and a uniform stochastic ADC. The result of these derivations shows that calculating ENOB from SNDR using the conventional equation causes a better-than-actual result in the case a uniform stochastic ADC.

A circuit is presented that halves the number of comparators required for a two-group stochastic flash ADC. In a two-group stochastic flash ADC, two Gaussian PDFs are shifted left and right by applying a global offset reference to the two groups of comparators. This creates a virtual uniform distribution of comparator offset between the two global offsets. Over half of the comparators fall outside of the virtual uniform distribution and are not used. The proposed circuit inverts the polarity of each comparator offset until it is within the useful range, creating a virtual uniform distribution of comparator offsets with few comparators wasted.

Scaling in CMOS technologies has made the application of traditional opamp topologies increasingly difficult. In the face of decreasing voltage headroom and intrinsic device gain, designers have employed techniques such as gain-boosting, correlated double sampling , and correlated level-shifting (CLS) [1] to maximize output swing for a given gain specification. Zero-crossing based circuits (ZCBC) remove the opamp altogether and use a comparator and current sources [2], which are more amenable to scaling and have proven capable of high efficiency, as in [3]. However, the open loop nature of ZCBC creates challenges for designs that must reliably track over process, voltage, and temperature. In this paper, we describe a hybrid CLS-opamp/ZCBC pipelined ADC that introduces techniques to improve accuracy, robustness, and power efficiency in scaled technologies. It incorporates CLS and a low power, small output swing double-cascoded telescopic opamp to achieve very high effective gain. A dynamically biased zero-crossing detector (ZCD) is introduced that increases the power efficiency of ZCBC designs.

A ones adder is an important circuit block that is required in many varying applications. This work proposes a design that largely relies on passive transmission-gate multiplexers. Many variations are suggested that can inherently generate a thermometer coded output or one-hot encoded output. The proposed structure has area and power that increases with order n 2 for a n number of inputs. A folding technique is then suggested that reduces the area/power to order n log(n). The folded passive linear counter also has a cell-based structure that aids in layout and makes it possible to be added to a digital standard cell library.

A 6-bit stochastic flash ADC is presented. By connecting many comparators in parallel, a reference ladder is avoided by allowing random offset to set individual trip points. The ADC transfer function is the cumulative density function of comparator offset. A technique is proposed to improve transfer function linearity by 8.5 dB. A test chip, fabricated in 0.18 mum CMOS, achieves ENOB over 4.9 b up to 18 MS/s with 900 mV supply and comparator offset standard deviation of 140 mV Comparators are digital cells to allow automated synthesis. Total core power consumption when fs = 8 MHz is 631muW.