350 results on '"Bertozzi, Davide"'
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2. Design Automation Beyond Its Electronic Roots: Toward a Synthesis Methodology for Wavelength-Routed Optical Networks-on-Chip
3. Assessing the Configuration Space of the Open Source NVDLA Deep Learning Accelerator on a Mainstream MPSoC Platform
4. Logic Programming approaches for routing fault-free and maximally-parallel Wavelength Routed Optical Networks on Chip (Application paper)
5. LNOI Wireless Switches Based on Optical Phased Arrays for On-chip Communication
6. Efficient Resource-Aware Neural Architecture Search with a Neuro-Symbolic Approach
7. Exploring the NBTI Aging and PVT effects on RRAM-based FPGA Multiplexers Performance
8. Assessing the Configuration Space of the Open Source NVDLA Deep Learning Accelerator on a Mainstream MPSoC Platform
9. Technology-Aware Drift Resilience Analysis of RRAM Crossbar Array Configurations
10. 4 × 4 Integrated Switches Based on On-Chip Wireless Connection through Optical Phased Arrays
11. DyAFNoC: Dynamically Reconfigurable NoC Characterization Using a Simple Adaptive Deadlock-Free Routing Algorithm with a Low Implementation Cost
12. Process-Voltage-Temperature Variations Assessment in Energy-aware Resistive RAM-based FPGAs
13. Reconfigurable Optical Wireless Switches for on-chip Interconnection
14. Exploring Process-Voltage-Temperature Variations Impact on 4T1R Multiplexers for Energy-aware Resistive RAM-based FPGAs
15. Keynote Talk: Ultra-Low Power and Flexible Asynchronous Interconnect Technology for Large-Scale Neuromorphic Computing
16. Transcriptional Stress by Camptothecin: Mechanisms and Implications for the Drug Antitumor Activity
17. Cost-Effective Contention Avoidance in a CMP with Shared Memory Controllers
18. On-chip wireless interconnection through reconfigurable optical phased arrays
19. An Asynchronous Soft Macro for Ultra-Low Power Communication in Neuromorphic Computing
20. Resource Management Policy Handling Multiple Use-Cases in MPSoC Platforms Using Constraint Programming
21. Hardware/Software Architecture for Real-Time ECG Monitoring and Analysis Leveraging MPSoC Technology
22. Allocation, Scheduling and Voltage Scaling on Energy Aware MPSoCs
23. Allocation and Scheduling for MPSoCs via Decomposition and No-Good Generation
24. Energy-Efficient Network-On-Chip Design
25. Energy-Reliability trade-Off for NoCs
26. The Challenge of Classification Confidence Estimation in Dynamically-Adaptive Neural Networks
27. The fast evolving landscape of on-chip communication: Selected future challenges and research avenues
28. Special Issue on Networks-on-Chip Again on the Rise: From Emerging Applications to Emerging Technologies
29. Reconfigurable on-chip wireless interconnections through optical phased arrays (Invited)
30. Design of reconfigurable on-chip wireless interconnections through Optical Phased Arrays
31. Silicon Validation of GALS Methods and Architectures in a State-of-the-Art CMOS Process
32. Wearout and Variation Tolerant Source Synchronous Communication for GALS Network-on-Chip Design
33. Reducing the abstraction and optimality gaps in the allocation and scheduling for variable voltage/frequency MPSoC platforms
34. A Fast and Accurate Technique for Mapping Parallel Applications on Stream-Oriented MPSoC Platforms with Communication Awareness
35. Cost-Effective and Flexible Asynchronous Interconnect Technology for GALS Systems
36. PSION+: Combining Logical Topology and Physical Layout Optimization for Wavelength-Routed ONoCs
37. Energy-efficient multiprocessor systems-on-chip for embedded computing: Exploring programming models and their architectural support
38. Topic 13: High-Performance Networks and Communication
39. MPARM: Exploring the Multi-Processor SoC Design Space with SystemC
40. Topic 13: High-Performance Networks and Communication : (Introduction)
41. Error control schemes for on-chip communication links: The energy-reliability tradeoff
42. Cross-Layer Hardware/Software Assessment of the Open-Source NVDLA Configurable Deep Learning Accelerator
43. Performance Analysis of Arbitration Policies for SoC Communication Architectures
44. Technology-Aware Communication Architecture Design for Parallel Hardware Platforms
45. Cost-Effective Contention Avoidance in a CMP with Shared Memory Controllers
46. Transcriptional Stress by Camptothecin: Mechanisms and Implications for the Drug Antitumor Activity
47. SystemC cosimulation and emulation of multiprocessor SoC designs
48. The Synchronization Challenge
49. Switch Models
50. Topology Exploration
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