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We propose for modeling and software implementation of proportional-integral-derivative controlled higher order phase-locked loop with low settling time acquisitions applicable to frequency modulated transceiver. The implementation has been done by inserting a proportionalintegral- derivative control block into the phase-locked loop during acquisition, where originally the output frequency/phase is controlled by a low pass loop filter. Simulation results show that the method can reduce the settling time up to 94%, 49% and 18% for 2nd, 3rd and 4th order phaselocked loop up to a frequency range of 0.9GHz. [ABSTRACT FROM AUTHOR]

We analyzed the phase noise of a 1.1 GHz phaselocked loop system for frequency synthesis. The system has been designed, fabricated and tested in the Instrumentation and Informatics Research Laboratory, Department of Electronics & Communication Technology, Gauhati University, Assam, INDIA. Details results of the analysis have been presented in this paper. [ABSTRACT FROM AUTHOR]

We model and simulate an analog phase-locked loop for frequency hopping spread spectrum based applications such as Bluetooth. The modeling and simulation method uses an analog phase-locked loop, consisting of multiplier, loop filter, voltage controlled oscillator and generates hopping carriers up to 2.502 GHz. The generated carrier frequency holds at a particular hop for a maximum dwell time of 50µS. The complete simulation program for the system is written in Turbo C. The MATLAB program is used for graphical analysis of simulated data. The simulation results show that the generated carriers settle around 60 µS for maximum hopping carrier frequency of 100 MHz. The measured carrier frequencies and settling times are found comparable with standard values and related works. [ABSTRACT FROM AUTHOR]

We have designed, developed and implemented a hierarchical web service using Java as programming language, apache tomcat as web server, MySQL as database server to study the performance of the web service. The web service has been tested by deploying it on Mercury Load Runner to study various attributes like load and performance of the service, scalability and reliability. In this paper, we will present in details the architecture of the service, its testing procedure and the result of different testing, performed on the service. [ABSTRACT FROM AUTHOR]

A prototype 40 KHz Phase-Locked Loop (PLL) has been designed and fabricated in Instrumentation and Informatics Research Laboratory, Department of Electronics and Communication Technology, Gauhati University, Assam, INDIA. The system has been tested using Agilent Spectrum Analyzer (Model: N9320; Frequency range: 9 KHz 3 GHz), Tektronix 100MHz arbitrary function generator (Model: AFG3012, 1GS/s) and Digital Phosphor Oscilloscope (DPO) (Model: Tektronix TDS 3052, 500MHz, 2.5 GS/Sec). This paper presents in details the experimental results and characterization of phase noise of the prototype PLL. [ABSTRACT FROM AUTHOR]