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The use of digital forensics tools has become common in typical crime investigations involving computing and communication devices. As with any evidence in criminal investigations, the preservation of digital evidence is of critical importance for the success of the investigation. Cryptographic Hash Functions (CHFs) are used by digital forensic tools to ensure the preservation of digital evidence during the acquisition and analysis of evidence. These tools make the use of the CHFs during the acquisition process to ensure that the created image of the evidence is accurate. The CHFs that are currently in use are serial in nature and can be time consuming when working with the large data sets. We propose a new parallel CHF transformation to speed up the image creation process by a factor of 6.5 over existing methods. We discuss the use of the parallel algorithm in the image creation process and compare the results with the existing sequential methods.

Emotions are an unstoppable and uncontrollable aspect of mental state of human. Some bad situations give stress and leads to different sufferings. One can’t avoid situation but can have awareness when body feel stress or any other emotion. It becomes easy for doctors whose patient is not in condition to speak. In that case person’s physiological parameters are measured to decide emotional status. While experiencing different emotion, there are also physiological changes taking place in the human body, like variations in the heart rate (ECG/HRV), skin conductance (GSR), breathing rate(BR), blood volume pulse(BVP),brain waves (EEG), temperature and muscle tension. These were some of the metrics to sense emotive coefficient. This research paper objective is to design and develop a portable, cost effective and low power embedded system that can predict different emotions by using Naive Bayes classifiers which are based on probability models that incorporate class conditional independence assumptions. Inputs to this system are various physiological signals and are extracted by using different sensors. Portable microcontroller used in this embedded system is MSP430F2013 to automatically monitor the level of stress in computer. This paper reports on the hardware and software instrumentation development and signal processing approach used to detect the stress level of a subject.To check the device's performance, few experiments were done in which 20 adults (ten women and ten men) who completed different tests requiring a certain degree of effort, such as showing facing intense interviews in office.

The purpose of this research effort is to develop a numerical model for a novel tri-material, gate stack engineered double gate MOSFET considering quantum confinement. While developing this model a combination of 2-D Poisson's equation and 1-D Schrodinger equation was used to obtain the potential profile and inversion charge across the complete silicon film. The proposed DG MOSFET structure has been implemented using Silvaco Atlas 2-D numerical device simulator to obtain the results for transfer characteristics, output characteristics and mobility variation. The results obtained indicate a trend of reduction in mobility and drain current while considering the quantum confined model of the device in comparison to the classical one.

In this paper we present low -cost, concurrent checking methods for multiple error detection in S -boxes of symmetric block ciphers. These are redundancy-based fault detection schemes. We describe some studies of parity based concurrent error detection in S -boxes. Probability of multiple error detection is analyzed for random data. In this work 48-input, 32-output substitution blocks are taken into consideration.

Power consumption has become the key differentiating factor for many different types of semiconductor products. This has led to recent advances in power management techniques to address power consumption in these products. These include power management techniques such as power gating, adaptive voltage and frequency scaling, and active body-bias that leverage voltage as a handle to manage power consumption. We look into an overview of these techniques and the resulting new challenges facing the functional validation of a system-on-a-chip.

Software applications are driving the growth of cloud computing era. The security of data over the networks is essential in order to enable cloud computing applications. The security of data is ensured through the use of various types of encryption algorithms. In the current cloud computing era we are witnessing the use of multi core processors which has enabled us to run security applications, simultaneously at both client and the server end. The encryption as well as decryption process of security algorithms is compute intensive and can take significant benefit from parallel implementations that can run on these multi core processors. Moreover these algorithms will consume more energy on uniprocessor systems due to the massive calculations they do, because there is a non-linear relationship between frequency of a core and power supply. This paper introduces a parallel version of Blowfish algorithm using Single Instruction Multiple Data model which is named as PBlock and its implementation on a Symmetric Multi Processor machine along with the results of performance gains that we have obtained on a number of benchmark examples.

RSA is one of the most popular Public Key Cryptography based algorithm mainly used for digital signatures, encryption/decryption etc. It is based on the mathematical scheme of factorization of very large integers which is a compute-intensive process and takes very long time as well as power to perform. Several scientists are working throughout the world to increase the speedup and to decrease the power consumption of RSA algorithm while keeping the security of the algorithm intact. One popular technique which can be used to enhance the performance of RSA is parallel programming. In this paper we are presenting the survey of various parallel implementations of RSA algorithm involving variety of hardware and software implementations., Comment: IJCSA February 2015

Emotions are an unstoppable and uncontrollable aspect of human reaction to an action. It is a proved mechanism that encompasses variation in emotions due to different acts, expectations, focus to goals, appraisal and resulting reactions. When human body experiences different emotions like fear, anger, sad, happiness then there is also change in different bio-signals which are flowing in human body. These biosignals are: Galvanic skin conductance (GSR), blood volume pulse (BVP), brain waves (EEG), muscle tension, temperature, and respiration. The overall objective of this work is to design and develop a low power, portable, and cost effective embedded system through which we can measure different parameters of autonomic nervous system (GSR/ temperature/Heart rate/EEG) of a person and display it on any of the output devices by using effective algorithm for stress recognition using learning systems. This portable embedded system will be using MSP430F2013 micro controller from Texas Instruments. This system will help measure different parameters such as GSR and BVP. This paper is also discusses an experiment which identifies the stimuli triggering off the emotional state of the person as a result of variations in the bio-signals.

Public-key infrastructure based cryptographic algorithms are usually considered as slower than their corresponding symmetric key based algorithms due to their root in modular arithmetic. In the RSA public-key security algorithm, the encryption and decryption is entirely based on modular exponentiation and modular reduction which are performed on very large integers, typically 1024 bits. Due to this reason the sequential implementation of RSA becomes compute-intensive and takes lot of time and energy to execute. Moreover, it is very difficult to perform intense modular computations on very large integers because of the limitation in size of basic data types available with GCC infrastructure. In this paper, we are looking into the possibility of improving the performance of proposed parallel RSA algorithm by using two different techniques simultaneously, first implementing modular calculations on larger integers using GMP library and second by parallelizing it using OpenMP on the GCC infrastructure. We have also analyzed the performance gained by comparing the sequential version with the parallel versions of RSA running on the GCC infrastructure.

In today's network-based cloud computing era, software applications are playing big role. The security of these software applications is paramount to the successful use of these applications. These applications utilize cryptographic algorithms to secure the data over the network through encryption and decryption processes. The use of parallel processors is now common in both mobile and cloud computing scenarios. Cryptographic algorithms are compute intensive and can significantly benefit from parallelism. This paper introduces a parallel approach to symmetric stream cipher security algorithm known as RC4. The algorithm is very popular and used in many key applications such the Wi-Fi connections, Skype, and Bit Torrent protocol systems. We present an efficient parallel implementation to the compute intensive PRGA that is pseudo-random generation algorithm portion of the RC4 algorithm and the resulted algorithm will be named as PARC4. The algorithm divides a message into fix sized large blocks and encrypts these blocks concurrently on multi core machine.

Hashing algorithms are used extensively in information security and digital forensics applications. This paper presents an efficient parallel algorithm hash computation. It's a modification of the SHA-1 algorithm for faster parallel implementation in applications such as the digital signature and data preservation in digital forensics. The algorithm implements recursive hash to break the chain dependencies of the standard hash function. We discuss the theoretical foundation for the work including the collision probability and the performance implications. The algorithm is implemented using the OpenMP API and experiments performed using machines with multicore processors. The results show a performance gain by more than a factor of 3 when running on the 8-core configuration of the machine.

We describe a power exploration methodology for data-dominated applications using a H.263 video decoding demonstrator application. The starting point for our exploration is a C specification of the video decoder, available in the public domain from Telenor Research. We have transformed the data-transfer scheme in the specification, and have optimized the distributed memory organization. This results in a memory architecture with significantly reduced power consumption. For the worst case mode using predicted (P) frames, memory power consumption is reduced by a factor of 7 when compared to the reference design. For the worst case mode using predicted and bi-directional (PB) frames, memory power consumption is reduced by a factor of 9. To achieve these results, we make use of our formalized high-level memory management methodology, partly supported in our ATOMIUM environment.

Online learning is fast becoming a preferred medium of learning. It is estimated that 6 million college students took at least one online course last year. Online learning in technical education is primarily delivered through pre-recorded videos. We will discuss a virtual learning system in the context of electronics engineering education. This learning system models the circuits as well as the instruments that are typically used in the labs to allow students to carry out the experiments in a virtual environment. We have extended the concept further to allow students to carry out the experiments on the web-browsers and devices of their choice. The simulations themselves are carried out utilizing cloud computing infrastructure such as those provided by Amazon and Microsoft while the use focuses on putting the experiments.

Summary form only given. The relative performance evaluation of decision alternatives is an important and challenging task for the sustainability of an organization. It is complicated by the measurements of tangible and intangible criteria reflecting the interests of different stakeholders involved in the decision making process and the lack of proper management tools to provide trade-offs analysis among decision alternatives. Trade-offs involves combinational valuation analysis using classical optimization tools. In this keynote address, a framework for the combinatorial valuation is proposed. It integrates performance criteria to align all stakeholders on a common set of desired goals and objectives. An optimization tool is used “called data envelopment analysis, DEA” to transform data intelligently into informed decisions to aid strategic performance managers. DEA is a non-parametric optimization approach to balance the costs and risks (resources) with benefits and opportunities (returns) to derive relative efficiency scores for the alternatives. The analysis identifies the set of efficient alternatives “called best practice benchmark”. It also provides rankings for the alternatives, and set target improvement levels for each inefficient alternative. The valuation framework is demonstrated for the management and measurement in four areas: people (1); organizations (2, 3); Systems and E-Government Services funded by the European Union (4) and the Qatar Foundation (5).

We look into the validation a power managed ARM Cortex A-8 core used in SoCs targeted for mobile segment. Low Power design techniques used on the chip include clock gating, voltage scaling, and power gating. We focus on the verification challenges faced in designing the processor core including RTL modeling of power switches, isolation, and level-shifting cells, simulation of voltage ramps, generation of appropriate control signals to put the device into various power states, and ensuring correct operation of chip in these states as well as during the transitions between these states.

WiMAX employs Orthogonal Frequency Division Multiple Access (OFDMA) as one of its physical access layer schemes. OFDMA is a derivative of Frequency Division Multiplexing (FDM). In OFDMA, data is first divided up into parallel chunks. The parallel data is then transmitted on several frequencies simultaneously, with the added twist that the signal is also spread out over time domain. For those designing WiMAX solutions, the verification of the latest wireless communication standard can be daunting. In this paper, we look at some of the challenges of physical access layer validation and discuss how SystemVerilog testbench constructs can be used to create random yet valid frames for WiMAX OFDMA to validate the physical access layer protocols.

We are at the crossroads of some fundamental changes that are taking place in the semiconductor industry. Power is a primary design criterion for bulk of the semiconductor designs now and a key reason behind the shift towards multicore designs as increase in power consumption limits increases in clock speed at the rate we have seen in the past.

We are at the crossroads of some fundamental changes that are taking place in the semiconductor industry. Power consumption has become one of the most important differentiating factors for semiconductor products due to a major shift in the market towards handheld consumer devices. Power is a primary design criterion for bulk of the semiconductor designs now. Power is a key reason behind the shift towards multi-core designs as increase in power consumption limits increases in clock speed at the rate we have seen in the past.

Symbolic representation of path delay-faults can achieve high degree of compaction relative to more explicit forms. Large numbers of path delay-faults exist in common digital circuits. Ordered binary decision diagrams (OBDDs) provide a convenient data structure to represent these large number of path delay faults during the process of fault simulation computing the path delay-fault coverage for a given delay test-set. We present some experimental results from applying these algorithms to common benchmark examples that demonstrate the viability of our approach.

A new algorithm for the efficient computation of path delay fault coverage for circuits with very large number of path delay faults has been presented. The directed acyclic graph representing a combinational circuit consists of a set of trees rooted at the fanout and output nodes. The algorithm uses a tree-based marking process to compute the path delay fault coverage of a given delay-test set in linear time and memory. The root of a tree is marked as used only when it has been tested with respect to the rising and falling path delay faults passing through all the leaves of the tree. The algorithm takes advantage of large tree structures found in most digital designs, to provide a reasonably accurate and very efficient method for the estimation of path delay fault coverage. Some results obtained using non-robust simulation of benchmark circuits suggest the viability and validity of our approach. >

Energy efficient computing is growing in demand as portable systems require energy efficiency in order to maximize the battery life. Memory power consumption is becoming an increasingly larger fraction of the total power consumption of a given system. In this paper, we provide data and insight into how the choice of cache parameters affects memory power consumption of video algorithms. We make use of memory traces generated as a result of running typical MPEG- 2 motion estimation algorithms to simulate a large number of cache configurations. The cache simulation data is then combined with on-chip and off-chip memory power models to compute memory power consumption. We provide a detailed study of how varying cache size, block size, and associativity affects memory power consumption. The configurations of particular interest are the ones that optimize power under certain constraints. We also study the role of process technology in these experiments. In particular, we look at how moving to a more advanced process technology for the on-chip cache affects optimal points of operation with respect to memory power consumption.© (1998) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Memory bandwidth is emerging as the fundamental impediment to higher performance and lower power computer and communication systems. In this paper, we present an analysis of memory bandwidth requirements for the H.263 video codec algorithms. We provide data and insight into how the choice of cache parameters affects external bandwidth requirements of video. We make use of memory traces generated as a result of running Telenor's H.263 video encoder and decoder software implementations to simulate a large number of cache configurations. In the area of analysis of video algorithms, this paper focuses on the following issues: we provide a study of how varying cache size, block size, associativity, replacement policy, and organization parameters such a split versus unified cache affects memory bandwidth requirements. A comparative study of encoder and decoder bandwidth requirements is presented. We also study various advanced encoding options provided with the H.263 standard in this light. Based on our study, we provide guidelines for traffic-directed memory system design.© (1998) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

We describe a power exploration methodology for data-dominated applications using a H.263 video decoding demonstrator application. The starting point for our exploration is a C specification of the video decoder, available in the public domain from Telenor Research. We have transformed the data transfer scheme in the specification and have optimized the distributed memory organization. This results in a memory architecture with significantly reduced power consumption. For the worst-case mode using predicted and bi-directional (PB) frames, memory power consumption is reduced by a factor of 9. To achieve these results, we make use of our formalized high-level memory management methodology, partly supported in our ATOMIUM environment.

The problem of modifying a synthesized circuit to improve its path sensitizability has been investigated. It is shown that a large number of paths, that cannot be sensitized using single-transition tests, are redundant paths and they can be removed by appropriate modification of the circuit. The effect of these modifications on area and performance of the circuit has been analyzed. For the paths which are neither redundant nor sensitizable using single-transition tests, it is shown that they can be sensitized using multiple-transition tests. Results obtained on some common benchmark examples suggest the validity and viability of this approach.