188 results on '"Bhattacharya, B.B."'
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2. Modeling interest rate cycles in India
3. Optimization of dilution and mixing of biochemical samples using digital microfluidic biochips
4. Bakreswar Geothermal Reservoir Revealed From Audio Magnetotelluric (AMT) Results
5. Sustaining India's High Economic Growth
6. Test pattern generation for droop faults
7. Approximate Matching of Digital Point Sets Using a Novel Angular Tree
8. Droop sensitivity of stuck-at fault tests
9. An Adaptive BIST Design for Detecting Multiple Stuck-Open Faults in a CMOS Complex Cell
10. Education, Skill Formation and India's Economic Development
11. Stacked Euler Vector (SERVE): A Gray-Tone Image Feature Based on Bit-Plane Augmentation
12. Testable Design of Digital Summation Threshold Logic Array for Synthesis of Symmetric Functions
13. An efficient scan tree design for compact test pattern set
14. Recovery-based real-time static scheduling for battery life optimization
15. Test pattern generation for power supply droop faults
16. Solving thermal problems of hot chips using Voronoi diagrams
17. Euler Vector for Search and Retrieval of Gray-Tone Images
18. CryptoScan: A Secured Scan Chain Architecture
19. Reconstruction of torn documents using contour maps
20. Approximate fingerprint matching using kd-tree
21. Testing of stuck-open faults in generalised Reed–Muller and EXOR sum-of-products CMOS circuits
22. Combinatorial Construction of the Orthogonal Concavity Tree of a Digital Object.
23. Layout-Aware Solution Preparation for Biochemical Analysis on a Digital Microfluidic Biochip.
24. Design and implementation of packet filter firewall using Binary Decision Diagram.
25. Waste-aware dilution and mixing of biochemical samples with digital microfluidic biochips.
26. Zero-aliasing space compaction of test responses using a single periodic output
27. Testing of Digital Microfluidic Biochips Using Improved Eulerization Techniques and the Chinese Postman Problem.
28. Derivation of Optimal Test Set for Detection of Multiple Missing-Gate Faults in Reversible Circuits.
29. A BDD-based approach to design power-aware on-line detectors for digital circuits.
30. Word Segmentation and Baseline Detection in Handwritten Documents Using Isothetic Covers.
31. Recognition of Hand-Drawn Graphs Using Digital-Geometric Techniques.
32. Optimal Reversible Logic Circuit Synthesis Based on a Hybrid DFS-BFS Technique.
33. A Novel Technology Mapping Technique for BDD-Based Circuits Using LEAP Cells.
34. Pin-Constrained Designs of Digital Microfluidic Biochips for High-Throughput Bioassays.
35. A Unified Solution to Scan Test Volume, Time, and Power Minimization.
36. A BDD-Based Design of an Area-Power Efficient Asynchronous Adder.
37. Synthesis of online testable reversible circuit.
38. Algorithms for biological cell sorting with a Lab-on-a-chip.
39. On the Detection of Missing-Gate Faults in Reversible Circuits by a Universal Test Set.
40. Accelerated Functional Testing of Digital Microfluidic Biochips.
41. Power-delay efficient technology mapping of BDD-based circuits using DCVSPG cells.
42. Characterization of Isothetic Polygons for Image Indexing and Retrieval.
43. Ranking of Optical Character Prototypes in a Large Database Using Isothetic Chord Lengths.
44. ICE: The Isothetic Convex Envelope of a Digital Object.
45. A Local Search Heuristic for Biobjective Intersecting Geometric Graphs.
46. Optimum Test Set for Bridging Fault Detection in Reversible Circuits.
47. Synthesis of single-output space compactors for scan-based sequential circuits
48. Low Power BDD-based Synthesis Using Dual Rail Static DCVSPG Logic.
49. Power Aware BDD-based Logic Synthesis Using Adiabatic Multiplexers.
50. A programmable built-in self-test for embedded DRAMs.
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