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This work proposes a Red Green Blue (RGB) image encryption and decryption digital system which uses random number sequence generators as core and also provides its internal architectural layout. SC-CNN (State Controlled Cellular Neural Network) based chaotic system which stands optimal in generating multi-scroll chaotic generators is inculcated in this system. The hyperbolic tangent function used in state equations of the chaotic generator is implemented via CORDIC (Coordinate Rotational Digital Computer) algorithm, which is an efficient algorithm to compute various trigonometric and hyperbolic functions. The above techniques are combined together to give hardware credibility to the scheme described. The randomness and the level of encryption are analyzed and validated with the help of multiple test inputs and corresponding encrypted outputs. The complete encryption and decryption flows are simulated using Xilinx Vivado 2019.1 and realized on FPGA (Field programmable gate array), Zynq 7 board, as the chosen device.

In this fast-growing world, where everyone is in hurry, speed has become a critical factor even in the electronics world. It’s not the answer but a fast answer is the need of the time. Artificial intelligence has touched almost all aspects of our lives. But the software implementation of machine learning algorithms has not been able to meet the expectations of solutions in nanoseconds, especially where neural networks with extensive calculations and arithmetic computations are involved. Multiplication and accumulation unit is an integral part of many signal processing and machine learning algorithms. Here we implement an arithmetic module based on distributed arithmetic imbibed with Residual Number System to prove the efficacy of hardware design over software implementation. The purpose is to exploit the parallelism property of FPGAs to accelerate the computations. The target device used is xc6vlx75t3ff484 from Virtex- 6 family in Xilinx. Simulations are tested in MATLAB and ModelSim with associated data to justify its feasibility.