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The last two decades have witnessed the gradual implementation of integrated science curriculum at the junior secondary level in China. However, in most provinces of China, the implementation is not as successful as expected. Challenges were reported, yet without fine-grained investigation, with respect to science teachers' instruction on integrated science. In this study, we aim to detect major problems by investigating the instruction of integrated science at the secondary level. Classroom observation focused on the teacher and student verbal behavior, teachers' competency of instructional organization, their presentation of instructional content, and the organization of learning activities. Findings revealed that students were provided with limited opportunities for participating and engaging in learning as science teachers were dominant in classroom talk. Teachers emphasized on the integration of knowledge within one subject (within-subject knowledge), but not the integration of knowledge between subjects (cross-subject knowledge), resulting in the unsuccessful instruction of the integrative content. What is more, teachers were inadequately competent in designing and delivering science, technology and society content, scientific inquiry and scientific experiments, which also affected the quality of instruction on integrated science.

This brief proposes a broadband noise-cancelling (NC) common-gate (CG)-common-source (CS) low-noise amplifier (LNA) with a passive network to improve the gain and noise performance simultaneously. In the CG-CS LNA with active feedforward, a current-bleeding (CBLD) circuit is required to provide the required DC current of the auxiliary amplifier, which introduces additional noise. In the proposed work, by adding a passive network at the output, the noise of the CBLD circuit can be made negligible. Moreover, the passive network also provides the shunt peaking to facilitate the gain and noise performance over the desired band. Fabricated in TSMC 40 nm CMOS technology, the measured results show the proposed LNA exhibits a gain of 16.5 – 19.5 dB, a noise figure (NF) of 3.2 – 5.2 dB from 2 to 12 GHz and an IIP3 of −3.5 dBm at 6 GHz. It consumes 9 mW from a 1.2 V supply and occupies a very compact die area of 0.092 mm2. [ABSTRACT FROM AUTHOR]

The high phase noise (PN) of CMOS millimeter-wave oscillators has encouraged the adoption of wide loop bandwidth for an integer- $N$ phase-locked loop (PLL). This article proposes a quadrature sampling phase-frequency detector (QS-PFD) to disengage the tradeoff between spur rejection and loop bandwidth. With the introduction of an auxiliary path for phase detection, the spur generated by the main path is canceled without incurring extra power or degrading the loop stability. The high gain of the QS-PFD attenuates its jitter contribution to the loop. The QS-PFD enables fast frequency detection and lock detection. Implemented in 40-nm CMOS technology, the proposed PLL shows a −75-dBc reference spur, −101.5-dBc/Hz PN at a 1-MHz offset, and a minimum integrated jitter of 121.9 fsrms (10 kHz–100 MHz) at 38.2 GHz with a division ratio of 128. The lock detection time is at the microsecond level. The proposed PLL consumes 23.6 mW from a 1.1-V power supply, leading to a figure of merit (FoM) of −245 dB. [ABSTRACT FROM AUTHOR]

A novel on-chip transformer configuration that gives an identical inductor pair, a higher individual coil self-resonant frequency (SRF), and excellent area efficiency are presented. This technique involves the unique way of inter-crossing the transformer's primary and secondary coils using multiple metallization layers. Truly symmetrical transformer configuration (100%) is demonstrated using minimum die size. Thus, a true 1:1 transformer has been realized on silicon. The effects of the parasitic within the transformer are represented by an equivalent-circuit model. Accurate semiempirical expressions describing the circuit components are provided based on the various layout parameters. Of all the transformer structures presented, the two designs occupying the minimum silicon area by a factor of > 2x have been selected for performance evaluation of the SRF, coupling coefficient, input impedance, quality factor, and inductance. The transmission line transformer mode has also been studied to examine the designs' performance in the differential mode. The second proposed design reported in this paper, with enhancements in $21 and k performance, is created by adding a unique routing technique onto the first proposed structure. The method presented is fully compatible with the standard foundry CMOS processes. The silicon data reported in this study are based on Chartered Semiconductor Manufacturing's 0.13-[micro]m RF CMOS technology node. Index Terms--Area efficiency, coupling coefficient, differential inductor, fully symmetrical transformer, identical inductor pair, inter-coil crossing, interleaved transformer, multidirectional coupling, RF CMOS, self-resonant frequency (SRF), stacked transformer, system-on-chip (SoC), transmission line transformer (TLT).

The IEEE 802.15.4 standard relaxes the requirements on the receiver front-end making subthreshold operation a viable solution. The specification is discussed and guidelines are presented for a small area ultra-low-power design. A subthreshold biased low-noise amplifier (LNA) has been designed and fabricated for the 2.4-GHz IEEE 802.15.4 standard using a standard low-cost 0.18-[micro]m RF CMOS process. The single-stage LNA saves on chip area by using only one inductor. The measured gain is more than 20 dB with an [S.sub.11] of -19 dB while using 630 [micro]A of dc current. The measured noise figure is 5.2 dB. Index Terms--Front-end, low-noise amplifier (LNA), low power, subthreshold.