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Summary: The intrinsic characteristics such as modular structure, filterless operation, and absence of DC‐link capacitor have made the modular multilevel converter (MMC) superior to the conventional multilevel converters. However, the submodule (SM) capacitor voltage balancing is crucial. This paper presents a voltage balance control method for MMC. The proposed method generates 2N + 1 levels (where N is the number of SMs per arm) which halves the step size of output voltage and improves the harmonic performance as compared to N + 1 level generation. It requires only one carrier per phase and no voltage and current measurements are needed for the implementation. Therefore, the proposed method makes the system cost‐effective and reduces the implementation issues related with carrier‐based methods substantially. It also alleviates the non‐uniform charge distribution problem with the phase disposition pulse width modulation (PDPWM) technique. Further, a detailed mathematical analysis is presented which enhances the understanding of balancing algorithm. In addition to this, the circulating current with 2N + 1 modulation is analyzed and a control technique is presented. The proposed voltage balancing method is simulated comprehensively in MATLAB/SIMULINK software and validated by the experimental results obtained from a laboratory prototype. [ABSTRACT FROM AUTHOR]

Modular multilevel converters (MMCs) have become prominent for high and medium power applications. The phase‐disposition pulse width modulation (PDPWM) technique is a carrier‐based method that generates good quality output. However, it has the inherent problem of uneven power distribution. Conventionally, this is solved by expensive voltage and current measurements. In this paper, a capacitor voltage balancing method is presented for MMC, which eliminates the need for voltage and current sensors. It also ensures uniform power distribution among the submodules (SMs). In addition, it needs only one carrier per phase, and one PWM reference, for either upper arm or lower arm to produce N + 1 level with N SMs per arm. The capacitor voltage balancing method is analyzed mathematically and verified for the MMC with two‐level half‐bridge SMs. The same method is also extended to the MMC with three‐level flying capacitor SMs. MATLAB/SIMULINK simulations and experimental results on a laboratory prototype are presented to verify the theoretical concepts. [ABSTRACT FROM AUTHOR]

This paper presents a module for single-phase multilevel inverter topology. The proposed module generates maximum 21-level bipolar output voltage with asymmetric sources without H-bridge. This results in reduction in filter cost and size. The module can be cascaded for high voltage applications. The same arrangement of voltage source magnitudes in first module is maintained in the remaining cascaded modules. The proposed topology is suitable for the applications like electric vehicle and emergency services like residences and hospitality industries, etc. A set of comparisons between the proposed and recently published topologies are provided to differentiate between them. The topology is simulated and verified in MATLAB/SIMULINK. A hardware prototype is developed in the laboratory for experimental confirmation with various conditions. [ABSTRACT FROM AUTHOR]

The huge untapped energy from ocean waves is one of the ideal solutions for world energy crisis. This paper proposes a linear-generator-based direct power conversion plant model to generate the electrical energy from ocean waves. The linear generator output is of variable magnitude and variable frequency in nature. In this paper, this variable output is converted to fixed dc voltage by using a diode bridge rectifier and a dc-link capacitor. The linear generator along with a diode bridge and a capacitor forms a wave power unit. These wave power units can be connected in series and parallel to meet the power ratings. A reliable multilevel inverter is fed from the wave power units to ensure uninterrupted tapping of power from this abundant renewable energy source. The reliable inverter operation is analyzed under open- and short-circuit faults in switches by reconfiguring the carrier waves of sine pulsewidth modulation during fault conditions. A fault detection algorithm using a single sensor at the output is also proposed to detect the faults in the switches of the proposed reliable inverter. The proposed plant model with a linear generator and a reliable inverter is simulated using ANSYS MAXWELL and MATLAB/Simulink. The plant model is tested using a programmable ac source for emulating the linear generator and the developed prototype of the diode bridge rectifier and the reliable multilevel inverter. [ABSTRACT FROM AUTHOR]

Summary: Bilevel inverters are replaced by multilevel inverters due to their capability of producing quality output voltage with low total harmonic distortion (THD). On the contrary, increase in number of semiconductor switches has questioned the reliability of the multilevel inverter topologies. To enhance the reliability, this paper proposes a single‐phase five‐level inverter topology with inherent fault‐tolerant feature. The proposed inverter can sustain faults in sources and semiconductor switches by amending the switching combinations. No healthy switch is needed to be bypassed during the fault to ensure the optimum utilization of the switches. An analysis on the basis of reliability, cost, and efficiency is carried out of the proposed inverter and compared with the existing topologies. To prove the claim, the experimental results of the developed hardware model is analyzed and compared with the simulation results of MATLAB/SIMULINK. [ABSTRACT FROM AUTHOR]

The reliability in inverters has gained a vast importance for their enhanced economic operation of the system. This paper proposes a three-phase reliable nine-level inverter with fault ride through capability. The proposed inverter synthesizes nine levels in the output with two asymmetrical voltage sources configured at a ratio of 1:3 under healthy operation. The inverter is analyzed for open circuit faults in switches. A reliability analysis is carried out for proposed inverter and compared with classical Cascaded-H Bridge. Combined control logic is implemented to control the inverter in accordance with the operating conditions. The circuit is operated with sinusoidal pulse width modulation under healthy condition, and it is made to operate with switching frequency optimal-based pulse width modulation (SFO-PWM) under fault cases, as it enhances fundamental DC value. The proposed inverter is simulated in MATLAB/SIMULINK, and the results are validated by an experimental setup. [ABSTRACT FROM AUTHOR]

Summary: Multilevel inverter topologies have received an increasing importance for their modular structures with better integration of renewable energy sources and reduced filtering requirements. But reliability is compromised in the process of decreasing the number of switches to produce the maximum number of voltage levels. This paper elevates a single‐phase fault‐tolerant inverter topology, which is modular in structure. The proposed inverter is analyzed for open‐ or short‐circuit faults in sources and open‐circuit faults in switches. Sine Pulse Width Modulation with multicarriers technique is used to control the circuit. The carrier signals are reconfigured under fault conditions based on levels to be generated by bypassing the faulted switch or source. The circuit is simulated in MATLAB/SIMULINK, and experimental setup is developed to claim the fault tolerance of proposed inverter. [ABSTRACT FROM AUTHOR]

The use of the dynamic voltage restorer (DVR) is preferred for the mitigation of voltage quality disturbances. In this paper, the real-time application of a 5-level transistor clamped H-bridge inverter for the single-phase DVR to realize the voltage sag mitigation is discussed. The controller is realized by comparing a sensitive load voltage with a reference voltage generated by the unit vector template method. MATLAB Simulink software is used to test the ability of the developed DVR by employing the in-phase and pre-sag compensation techniques. In addition, an experimental evaluation is performed in real time to observe the compensation capability of a 5-level transistor clamped H-bridge DVR. The design details of developed DVR are discussed, a prototype of DVR is also built in the laboratory. For verification of the capability of proposed DVR topology for voltage sag mitigation, experimental findings are presented. [ABSTRACT FROM AUTHOR]

This paper presents simplified techniques for the space vector modulation (SVM) of any n-level multilevel inverter. Three techniques have been presented to simplify the identification of the nearest three vectors to the reference vector. The first two techniques are based on resolving the multilevel inverter space vector diagram into appropriate two-level hexagons. This results in simplification of the multilevel SVM problem into a two-level SVM problem. The third technique is an algorithm-based technique which makes use of a 60°-spaced gh coordinate system to perform the SVM of a multilevel inverter. Switching sequence design for all the three techniques is presented with the aim of minimization of the device switching frequency. Simulation and experimental results have been provided to verify the feasibility of the proposed techniques. Simulation results are provided for up to 21-level cascaded H-bridge (CHB) inverters, while the experimental verification is done on a five-level laboratory prototype. Although only the CHB inverter is considered in this study, the proposed techniques are perfectly general and can be applied to all types of multilevel inverters, and are extendable to any number of levels. [ABSTRACT FROM AUTHOR]

In this paper, a single phase modified switched-diode topology for both symmetrical and asymmetrical cascaded multilevel inverters is presented. It consists of a Modified Switched-Diode Unit (MSDU) and a Twin Source Two Switch Unit (TSTSU) to produce distinct positive voltage levels according to the operating modes. An additional H-bridge synthesizes a voltage waveform, where the voltage levels of either polarity have less Total Harmonic Distortion (THD). Higher-level inverters can be built by cascading MSDUs. A comparative analysis is done with other topologies. The proposed topology results in reductions in the number of power switches, losses, installation area, voltage stress and converter cost. The Nearest Level Control (NLC) technique is employed to generate the gating signals for the power switches. To verify the performance of the proposed structure, simulation results are carried out by a PSIM under both steady state and dynamic conditions. Experimental results are presented to validate the simulation results. [ABSTRACT FROM AUTHOR]

In this paper, a simplified nearest level control balancing method for modular multilevel converter is presented. The proposed method neither requires individual sorting of the submodule voltages nor the redundancy of the switching states. Once the sorting of the submodules is done on the basis of the number of the submodules to be switched on, the identifications of the submodules can be carried out throughout the stages of the implementation of the this method. The proposed method also does not require the individual submodule status in the gate pulse generation stage. The gate logic in the presented method can be implemented with the help of the switching states of the voltage levels. Those simplifications and removing of the some of the stages by the proposed balancing method may ease and lead to the less processor time at the implementation level. The pictorial presentation further helps in consolidating the understanding of the different stages of the method. Rigorous simulations are carried out for open and one of the prominent closed-loop applications, i.e., modular multilevel converter-based high-voltage direct current to demonstrate the validity and effectiveness of the proposed simplified balancing method under normal and emergency conditions. [ABSTRACT FROM AUTHOR]

This paper proposes conjugate gradient back-propagation based artificial neural network for real time power quality assessment. The novel real time voltage sag and swell detection, classification scheme using artificial neural network is presented. The ANN is trained in MATLAB using voltage sampled signal data and corresponding parameters of the neural network are utilized to implement in LabVIEW in real time sag swell detection and classification. The Levenberg Marquardt, the resilient back-propagation and conjugate back-propagation algorithm performance is evaluated in MATLAB to find the best neural network for real time application. Among these three back-propagation algorithms, conjugate gradient algorithm has better performance for real time power quality monitoring. The mathematical model of Conjugate gradient back-propagation neural network is implemented in LabVIEW. Real time voltage signals of sag and swell for different time duration and magnitude, intensity are acquired from hardware experimental setup. Hardware setup mainly consists of single phase 230 V voltage source, microcontroller, dimmerstat and solid state relays. Voltage signals of sag and swell are sensed using high precision voltage sensor. Data acquisition system is used to acquire the signal from voltage sensor. The output of data acquisition system is given to the personal computer with LabVIEW. The proposed monitoring system also detects odd and even harmonic components in the voltage signal acquired using FFT. Real time hardware results obtained using proposed power quality monitoring system for detection of voltage sag, swell and harmonics claims the suitability, robustness and adaptability to monitor power quality issues. [ABSTRACT FROM AUTHOR]

An isolated four channel dc/dc converter with zero voltage switching is proposed as the front-end of multiple inverter structures to integrate renewable and other low voltage energy sources to micro grids. The interleaving technique is adopted to connect each module of proposed converter to a common dc source. This dc source can be a fuel cell stack, PV panels, battery, or any other low voltage dc source. All four channels are interleaved and a phase shift of $90^{\circ }$ is provided between the gate signals of each channels, which reduces the input current ripple. The output port of the proposed converter provide four isolated and regulated dc voltages. These isolated dc sources can be connected in series or parallel or series-parallel manner to obtain required dc-link voltage of various inverter structure. Issues like capacitor voltage balancing of diode clamped multilevel inverters can overcome through the proposed converter. By incorporating a coupled inductor for isolation and energy storage along with voltage multiplier circuit, the proposed converter can achieve higher voltage step up with lower turns ratio and lower voltage stress at moderate duty ratio. Hence, mosfets of low voltage rating (low $R_{DS}(\text{ON})$ ) can be utilized to reduce conduction loss. A 2 kW prototype of the proposed interleaved dc/dc converter is developed and tested with diode clamped three-level inverter, five-level inverter, and three-phase two-level inverter to verify the design. [ABSTRACT FROM AUTHOR]

In this paper, an improved Space Vector Modulation (SVM) based fault tolerant operation on a nine-level Cascaded H-Bridge (CHB) inverter with an additional backup circuit is proposed. Any type of fault in a power converter may result in a power interruption and productivity loss. Three different faults on H-bridge modules in all three phases based on the SVM approach are investigated with diagrams. Any fault in an inverter phase creates an unbalanced output voltage, which can lead to instability in the system. An additional auxiliary unit is connected in series to the three phase cascaded H-bridge circuit. With the help of this and the redundant switching states in SVM, the CHB inverter produces a balanced output with low harmonic distortion. This ensures high DC bus utilization under numerous fault conditions in three phases, which improves the system reliability. Simulation results are presented on three phase nine-level inverter with the automatic fault detection algorithm in the MATLAB/SIMULINK software tool, and experimental results are presented with DSP on five-level inverter to validate the practicality of the proposed SVM fault tolerance strategy on a CHB inverter with an auxiliary circuit. [ABSTRACT FROM AUTHOR]

This paper presents a novel approach to improve the power factor (PF) and reduce the harmonics generated by an adjustable-speed drive (ASD). A high-frequency (HF) current injection technique is used to improve the PF and harmonic performance. The HF current at the same switching frequency (33 kHz) is injected into the input of a front-end rectifier from the output of an HF inverter. The main feature of the circuit is that it does not require any additional active devices for current injection. The inverter driving the induction motor is operated using a sinusoidal pulsewidth-modulation technique. The circuit simulation and experimental prototype results are presented for 67-hp (50 kW) and 3-hp three-phase induction motors, respectively. [ABSTRACT FROM AUTHOR]