22 results on '"Borowiak, C."'
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2. Impact of local back biasing on performance in hybrid FDSOI/bulk high-k/metal gate low power (LP) technology
3. Impact of a 10 nm ultra-thin BOX (UTBOX) and ground plane on FDSOI devices for 32 nm node and below
4. Impact of laser anneal on NiPt silicide texture and chemical composition.
5. 450 GHz <tex>$f_{\text{T}}$</tex> SiGe:C HBT Featuring an Implanted Collector in a 55-nm CMOS Node
6. 450 GHz $f_{\text{T}}$ SiGe:C HBT Featuring an Implanted Collector in a 55-nm CMOS Node
7. Impact of 45° rotated substrate on UTBOX FDSOI high-k metal gate technology
8. Impact of substrate orientation on Ultra Thin BOX Fully Depleted SOI electrical performances
9. Impact of local back biasing on performance in hybrid FDSOI/bulk high-k/metal gate low power (LP) technology
10. Crystallization study of “melt quenched” amorphous GeTe by transmission electron microscopy for phase change memory applications
11. Microscopy needs for next generation devices characterization in the semiconductor industry
12. UTBOX and ground plane combined with Al2O3 inserted in TiN gate for VT modulation in fully-depleted SOI CMOS transistors
13. A solution for an ideal planar multi-gates process for ultimate CMOS?
14. Impact of a 10nm ultra-thin BOX (UTBOX) and ground plane on FDSOI devices for 32nm node and below
15. Hybrid Localized SOI/bulk technology for low power system-on-chip
16. Efficient multi-VT FDSOI technology with UTBOX for low power circuit design
17. Localized SOI logic and bulk I/O devices co-integration for Low power System-on-Chip technology
18. First CMOS integration of ultra thin body and BOX (UTB2) structures on bulk direct silicon bonded (DSB) wafer with multi-surface orientations
19. Hybrid FDSOI/bulk High-k/metal gate platform for low power (LP) multimedia technology
20. Impact of a 10nm Ultra-Thin BOX (UTBOX) and Ground Plane on FDSOI devices for 32nm node and below
21. 300 mm Multi Level Air Gap Integration for Edge Interconnect Technologies and Specific High Performance Applications
22. Localized SOI logic and bulk I/O devices co-integration for Low power System-on-Chip technology.
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