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The most widely used asymmetric cipher is ECC. It can be applied to IoT applications to offer various security services. However, a wide range of sectors have been investigated for applying ECC. The field of elliptic curve cryptographic processors for GF (2191) has received less attention. This study presents a low-resource, high-efficiency architecture for a 191-bit ECC processor. This design uses a novel hybrid Karatsuba multiplier for the multiplication of finite fields. For GF (2191), the Quad-Itoh-Tsuji algorithm has been altered to provide a small-size inversion unit. PlanAhead software synthesizes the CPU, which is then implemented on several Xilinx FPGAs. With savings in slice consumption ranging from 16 to 43 percent, the implemented design is the most restricted compared to the current designs. Compared to previously published designs, it is 3.8–1000 times faster. The elliptic curve scalar multiplication on the Virtex-7 FPGA is computed in $7.24~\mu $ s. Additionally, the proposed design achieves savings in area-time products of 77 to 90 percent. It may be beneficial for IoT edge devices. It utilizes 3120 mW of power for the operation. A state-of-the-art comparison based on the figure of merit (FoM) reveals that the proposed design outclasses the newest designs by a large margin. It also exhibits a throughput of 138.121 Kbps.

The phenomenal growth of resource constrained devices in IoT set ups has motivated the researchers to develop solutions for securing information flow. In this paper, we present a compact and efficient field programmable gate array (FPGA) implementation of AES with 32-bit data-path named, AES-32GF. The implementation is carried out on different Xilinx FPGAs. In FPGAs, utilization of slices and look up tables (LUTs) reflect on the compactness of the design. Numerical results show that lesser resources are required with smaller data path in comparison with the original standard. With the help of data path compression and Galois field implementation of the s-box resource consumption is minimized. S-box is the most resource consuming component in the AES structure. In our implementation, Artix-7 series FPGA for the same. It results in significant resource savings. In comparison to unrolled AES-128 architecture, it achieves 87 % resource savings. With 595 slices and 2.004 Gbps throughput, AES-32GF cipher achieves an efficiency of 3.37 Mbps/slice. It outperforms other designs in terms of efficiency. • A compact and efficient FPGA implementation of AES with 32-bit data-path has been proposed. • The proposed design utilizes data path compression and Galois field implementation of the s-box to minimize resource consumption. • With 595 slices and 2.004 Gbps throughput, AES-32GF cipher achieves an efficiency of 3.37 Mbps/slice.

A comprehensive experimental study to analyze the security performance of a WLAN based on IEEE 802.11 b/g/n standards in various network scenarios is presented in this paper. By setting-up an experimental testbed we have measured results for a layered security model in terms of throughput, response time, encryption overheads, frame loss and jitter. Through numerical results obtained from the testbed, we have presented quantitative as well as realistic findings for both security mechanisms and network performance. It establishes the fact that there is always a tradeoff between the security strength and the associated network performance. It is observed that the non-roaming network always performs better than the roaming network under all network scenarios. To analyze the benefits offered by a particular security protocol a relative security strength index model is demonstrated. Further we have presented the statistical analysis of our experimental data. We found that different security protocols have different robustness against mobility. By choosing the robust security protocol, network performance can be improved. The presented analysis is significant and useful with reference to the assessment of the suitability of security protocols for given real time application.

One of the important aspects of seamless communication for ubiquitous computing is the dynamic selection of the best access network for a multimodal device in a heterogeneous wireless environment. In this paper, we consider available bandwidth as a dynamic parameter to select the network in heterogeneous environments. A bootstrap approximation based technique is firstly utilized to estimate the available bandwidth and compare it with hidden Markov model based estimation to check its accuracy. It is then used for the selection of the best suitable network in the heterogeneous environment consisting of 2G and 3G standards based wireless networks. The proposed algorithm is implemented in temporal and spatial domains to check its robustness. The numerical results show that the proposed algorithm gives improved performance in terms of estimation error (less than 15%), overhead (varies from 0.45% to 72.91%) and reliability (approx. 99%)as compared to the existing algorithm.