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We propose a power e?cient branch predictor for the Cell SPU, which normally depends on compiler inserted hint instructions to predict taken branches. We designed four predictors all using Branch History Table (BHT) to store the Branch Target Address and the prediction, which is computed using a bimodal counter. The Simple Bimodal Predictor (SBP) predecodes instructions in the Instruction Line Bu?er and accesses the BHT only for a branch instruction and ignores hints. For the second design, four ways to combine hints with the SBP are studied, by not or partially overruling hints by the predictor. We also introduce Branch Warnings (BW). The SPU only accesses the predictor when a BW or a hint is executed and hints can be overruled. The Aggressive Bimodal Predictor is an aggressive implementation of the SBP that starts predicting when instructions are fetched from local store. It is not designed for energy e?ciency but to investigate the maximum possible speedup for a branch predictor not using hints. Results show that a SBP in combination with overruling hints (SBP-OH-NLS) and a 256-entry BHT can have a speedup of 18.8%. The Branch Warning predictor is the fastest in some occasions, however a non optimal compiler makes it the worst for others. The SBP has the lowest performance overall. The estimated extra power needed for the SBP and SBP-OH-NLS is about 1% of the total SPE power and even less for the BW-OH-NLS. The energy-delay product is reduced the most for the SBP-OH-NLS., Computer Engineering, Electrical Engineering, Mathematics and Computer Science

We propose a power e?cient branch predictor for the Cell SPU, which normally depends on compiler inserted hint instructions to predict taken branches. We designed four predictors all using Branch History Table (BHT) to store the Branch Target Address and the prediction, which is computed using a bimodal counter. The Simple Bimodal Predictor (SBP) predecodes instructions in the Instruction Line Bu?er and accesses the BHT only for a branch instruction and ignores hints. For the second design, four ways to combine hints with the SBP are studied, by not or partially overruling hints by the predictor. We also introduce Branch Warnings (BW). The SPU only accesses the predictor when a BW or a hint is executed and hints can be overruled. The Aggressive Bimodal Predictor is an aggressive implementation of the SBP that starts predicting when instructions are fetched from local store. It is not designed for energy e?ciency but to investigate the maximum possible speedup for a branch predictor not using hints. Results show that a SBP in combination with overruling hints (SBP-OH-NLS) and a 256-entry BHT can have a speedup of 18.8%. The Branch Warning predictor is the fastest in some occasions, however a non optimal compiler makes it the worst for others. The SBP has the lowest performance overall. The estimated extra power needed for the SBP and SBP-OH-NLS is about 1% of the total SPE power and even less for the BW-OH-NLS. The energy-delay product is reduced the most for the SBP-OH-NLS., Computer Engineering, Electrical Engineering, Mathematics and Computer Science