19 results on '"Briggs, Basoene"'
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2. MOL patterning challenges in scaled SRAM with vertical Surrounding Gate Transistors (SGT)
3. Patterning challenges and opportunities in nanosheet device architectures
4. Recess metrology challenges for 3D device architectures in advanced technology nodes
5. Buried power rail integration for CMOS scaling beyond the 3 nm node
6. (Invited) Cutting-Edge Epitaxial Processes for Sub 3 Nm Technology Nodes: Application to Nanosheet Stacks and Epitaxial Wrap-Around Contacts
7. Engineering high quality and conformal ultrathin SiNx films by PEALD for downscaled and advanced CMOS nodes
8. Buried Power Rail Integration With FinFETs for Ultimate CMOS Scaling
9. Recess metrology challenges for 3D device architectures in advanced technology nodes
10. Defect Mitigation in Area‐Selective Atomic Layer Deposition of Ruthenium on Titanium Nitride/Dielectric Nanopatterns
11. Electrical comparison of iN7 EUV hybrid and EUV single patterning BEOL metal layers
12. Patterning challenges in 193i-based tip to tip in N5 interconnects
13. Enabling CD SEM metrology for 5nm technology node and beyond
14. Electrical comparison of iN7 EUV hybrid and EUV single patterning BEOL metal layers.
15. Electrical comparison of iN7 EUV hybrid and EUV single patterning BEOL metal layers
16. Atomic Layer Deposition of Ruthenium with TiN Interface for Sub-10 nm Advanced Interconnects beyond Copper
17. Recess metrology challenges for 3D device architectures in advanced technology nodes.
18. Ruthenium metallization for advanced interconnects.
19. Enabling CD SEM metrology for 5nm technology node and beyond
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