Search

Ultra-violet (UV) laser annealing (LA) is a promising technology that is being investigated for next-generation CMOS processing. UV-LA’s unique capability of activating dopants very near to the surface due to the very shallow penetration depth can be critical for achieving very low-contact resistivity materials and structures. Here we present a detailed analysis of the effects of UV-LA on very highly As-doped material. Physical and chemical data-sets (SIMS, XTEM and FFTM) are compared with the electrical depth profiles obtained using Differential Hall Effect Metrology (DHEM).

Electrical properties and microstructure of phosphorus (P) implanted p-type Si substrates were evaluated by four-point probe (4PP), Differential Hall Effect Metrology (DHEM), secondary ion mass spectrometry (SIMS) and transmission electron microscopy (TEM) techniques, after RTA 750–950°C and CO2 laser 120–140W annealing. When RTA temperature was increased, defect concentration at a-Si/c-Si interface gradually disappeared. For CO2 laser annealing, defects were found to aggregate at the end of range (EOR) region. Sheet resistance (Rs) values decreased significantly with increasing RTA temperature due to defects disappearing at EOR. Rs did not change appreciably for the CO2 laser annealing case. The dopant activation ratio was less than 50% below RTA temperature of 850 °C, and it increased to 70% at 950 °C. For CO2 laser annealing, the activation ratio could reach to over 80% regardless of the laser power. The highest active concentration and the lowest resistivity or mobility were found to be within the top 20 nm region of the surface. Although RTA annealing conditions influenced dopant diffusion and the resulting electrical property depth profiles significantly, depth profiles did not change much with changes in CO2 laser power level. It was demonstrated that DHEM data in conjunction with SIMS and TEM data can be successfully employed to evaluate, in detail, the electrical properties of ultra-shallow junctions for metal oxide semiconductor field effect transistor (MOSFET) applications.

Differential Hall Effect Metrology (DHEM) technique was used to study dopant activation in n-Si and p-SiGe materials. n-type Si samples were prepared by P ion implantation followed by RTA at temperatures ranging from 750ºC to 950ºC. Junction depth and dopant activation through the layers were correlated with process parameters. Using DHEM mobility profiles, a correlation was also established between the EOR defect location and their elimination through high temperature annealing. DHEM resistivity depth profile displayed increased resistivity in the surface region of B-doped SiGe (50%) epi layer. This electrical behavior is in excellent agreement with expected reduction in B incorporation as strain-relaxation occurs towards the free surface. These results demonstrate prime importance of DHEM capabilities for engineering of advanced contacts.

Differential Hall effect metrology (DHEM) provides depth profiles of all critical electrical parameters through semiconductor layers at nanometer-level depth resolution. This article describes the relatively new method and shows how it is used to measure mobility and carrier concentration profiles in different materials and structures.

Contact resistivity at the metal-semiconductor interface is a strong function of the carrier concentration in the near surface. For next generation 2D/3D MOSFET transistors, industry has been investigating very highly doped materials (>1x1021cm-3) approaching alloy concentrations in Silicon and various Silicon-Germanium materials. All the while, contact development in Ge NMOS has favored co-doping approaches. Regardless of the material system, it is very important to accurately measure near-surface dopant activation. In this paper, we use Differential Hall Effect Metrology (DHEM) implemented on the ALPro™ tool to characterize the activation profiles in both materials. The method employs electrochemical means of reducing the electrically active thickness of a semiconductor film and determining the sheet resistance and mobility of the thinned down layer using Van der Pauw/Hall effect type measurements. By repeating this process and using differential equations, depth profiles of mobility and carrier concentration are obtained [1] at sub-nm resolutions. It is difficult to achieve high n-type dopant activation in Ge. Point defects in Ge are known to behave as acceptor sites and reduce the overall free electron density, particularly near the surface. Minimization of these defects is essential to achieving high performance Ge NMOS. Accurate analysis of dopant activation within 5 nm of the surface is critical to understanding effectiveness of various process steps on improving contact resistance. We have previously published a study on the effect of Ge co-doping with Sb and P on near-surface dopant activation. In Ge with only P-doping it was found that only ~5x1018cm-3 or 5% of the total surface dopants (~1x1020cm-3) were electrically active. With Sb as a co-dopant, the active electron concentration increased to ~2x1019cm-3 with a similar P chemical concentration. Prior work has shown similar increases in activation with co-doping but did not capture the significant decrease in electron concentration by 4x within 10 nm of the surface. Here, we further study the effects of the implantation and annealing processes on near-surface dopant activation in n-type Ge. Samples were prepared by growing 3 µm thick epi-Ge layers on Si substrates. Sample 1 was capped with 20 nm SiO2 and Sample 2 was capped with 20 nm Al2O3 to minimize implant damage and control implant depth. Both samples were implanted first with Sb (dose: 6x1014cm-2, energy: 65 keV) followed by P (dose: 6x1014cm-2, energy: 90 keV). Post-implant anneal was done at 500°C for 10 s in N2 to activate the dopants. ALProTM and SIMS measurements were done to characterize active dopant concentration and total chemical dopant concentration, respectively. The Al2O3 capped sample (Sample 2) showed significantly lower carrier concentration than the SiO2 capped sample (Sample 1) throughout the depth of the profile (Figure 1). Carrier concentration at the surface was lower by nearly an order of magnitude, decreasing from ~2x1019cm-3 to ~2x1018cm-3. Additionally, the peak concentration decreased from 1x1020cm-3 to 5x1019cm-3 at a depth of ~30 nm in both cases. The variations in the carrier profile for the Al2O3 capped sample also indicate greater process variation. SIMS profiles show that there is significant diffusion of Al into the Ge matrix after implant and anneal. Al chemical concentration is 1x1020cm-3 at the Ge surface and steadily decays up to a depth of more than 300 nm. This indicates that there is significant damage caused during the implantation process and the activation anneal is not enough to remove these defects. Al atoms then diffuse from the Al2O3 capping layer into the highly defective Ge substrate. Al is a p-type dopant in Ge and counter-dopes the Sb and P implants to reduce overall electron concentration in Sample 2. It is important to note the high resolution DHEM technique was able to resolve this important phenomenon right near the surface of the material. Additionally, we present early data on very highly phosphorus-doped (~1x1021cm-3) epitaxial silicon thin films grown on Si substrates. In very highly doped Silicon materials, the effect of near-alloy levels of dopant in the matrix on dopant deactivation is not well-known. Samples were obtained with different levels of dopant concentration above ~1x1021cm-3and different anneal temperatures. It was found that near-surface activation in these un-capped samples led to a lowering of activation in the References: Abhijeet Joshi and Bulent Basol, “ALPro System: An Electrical Profiling Tool for Ultra-thin Film Characterization”, 2017 Frontiers of Characterization and Metrology for Nanoelectronics (FCMN), pgs.170-172. Figure 1

Three-dimensional (3D) CMOS technology encourages the use of UV laser annealing (UV-LA) because the shallow absorption of UV light into materials and the process timescale typically from nanoseconds (ns) to microseconds (us) strongly limit the vertical heat diffusion. In this work, us UV-LA solid phase epitaxial regrowth (SPER) demonstrated an active carrier concentration surpassing 1 x 10^21 at./cm^-3 in an arsenic ion-implanted silicon-on-insulator substrate. After the subsequent ns UV-LA known for improving CMOS interconnect, only a slight (about 5%) sheet resistance increase was observed. The results open a possibility to integrate UV-LA at different stages of 3D-stacked CMOS., Comment: Accepted manuscript for Applied Physics Express (IOP science)

In advanced node transistors the contact resistance dominates parasitic resistance and negatively impacts power consumption and speed. Therefore, there is considerable efforts directed towards reducing source/drain (S/D) contact resistivity below 10 −9 ohm-cm 2 level. Increasing the carrier concentration in S/D requires development of doping and annealing techniques and evaluation of dopant activation, especially in the near-surface regions of the films. In this contribution, we present a study of active dopant depth profiles through n-type highly doped Si films using Differential Hall Effect Metrology (DHEM) technique.

Heavily n-doped epitaxially grown Si layers are of great importance for source/drain (S/D) application in advanced node nMOS devices. For contact resistivity reduction, the dopant activation level is very important. Various techniques are being used to evaluate dopant activation in Si:P layers. Among these two methods are Scanning Spreading Resistance Microscopy (SSRM) and Differential Hall Effect Metrology (DHEM). SSRM uses an atomic force microscope equipped with a hard conductive probe that is scanned in contact mode on the cross-sectioned sample’s surface and measures spreading resistance. Measured resistance values as a function of depth are converted into resistivity and carrier concentration depth profiles using calibration measurements and conversion relationships. DHEM provides depth profiles of mobility, resistivity and carrier concentration through a semiconductor layer by making successive sheet resistance (Rs) and Hall voltage measurements using Hall effect/Van der Pauw techniques, as the electrically active thickness of the layer is reduced through successive oxidation steps. Controlled oxidation is achieved by electrochemical anodization. Data collected can then be processed to yield the depth profiles. In this contribution we have carried out SSRM and DHEM measurements on Si:P epi layers subjected to different processing conditions including annealing and ohmic contact fabrication. Secondary Ion Mass Spectrometry (SIMS) was used to measure the total (active + inactive) dopant profiles through the films. Effects of these processes on dopant diffusion and activation were studied and the results from DHEM and SSRM were compared. In-situ phosphorus (P) doped Si epi-layers were grown over 300mm diameter boron doped monitor wafers. While one set was kept as the reference, a second set was treated by a spike-annealing process at 1000 °C. In a third set a Ti/TiN contact fabrication process was carried out and the contact was removed before analysis. In the fourth set contact process was applied to the spike annealed wafer before removal of the Ti/TiN layers. Bulk sheet resistance measurements were made using 4-point probe (4PP) for all the samples. SSRM measurements were carried out at IMEC. Cross-shaped Van der Pauw test-patterns were formed on 8mmx8mm areas on the samples and DHEM measurements were performed at ALP. Figure below shows the dopant depth profiles obtained by SIMS and the carrier concentration profiles from DHEM and SSRM techniques for samples D02 (as deposited Si:P) and D03 (spike annealed). One can make some general observations from the data in this figure. The total dopant concentration as measured by SIMS is ~ 1.4E21/cm3. There is only a small difference in the total dopant distribution profiles (SIMS) between the as deposited sample and the spike annealed sample. However, the spike annealed sample shows much higher dopant activation as measured by DHEM. Carrier concentration is ~2.5x higher in sample D03 (~5E20/cm3) compared to sample D02 (~2E20/cm3). Activation levels measured by SSRM, however, are lower for both samples, and the peak carrier concentration value increases only slightly upon spike annealing, going from ~2E20/cm3 in sample D02 to ~2.2E20/cm3 in sample D03. DHEM clearly indicates the sharp interface between the p-type substrate and the n-type epi-layer and its depth calibration agrees well with the expected thicknesses of the epi layers. The tail of the SSRM data is much more graded. Data from other samples will be presented and discussed in the final manuscript. Figure 1

For undoped

As advanced CMOS technology scaling goes beyond 7nm node, contact resistivity becomes an important factor influencing device performance. Approaches to reduce contact resistivity involve advanced doping techniques that yield very high degree of dopant activation at the semiconductor layers comprising the source and drain regions. These approaches include in-situ heavily doped epi layers and ion implantation followed by advanced annealing techniques. Irrespective of the approach used in wafer processing, accurate analysis of dopant activation within the top few nanometers of the surface is critical to understanding the effectiveness of such processes on improving contact resistivity. Similarly, correlation of mobility depth profile to defectivity in the layers helps one to understand how process variables may affect the ultimate electrical properties. Differential Hall Effect Metrology (DHEM) is the only method that can provide mobility and active dopant depth profiles through semiconductor layers at sub-nm resolution. The method employs electrochemical means of reducing the electrically active thickness of a semiconductor film and determining the sheet resistance and mobility of the thinned down layer using Van der Pauw/Hall effect type measurements [1]. In this work we characterized an ion implantation/annealing process cycle using DHEM and TEM studies. The sample was a p-type Si wafer ion implanted with P (10keV, 2E15cm-2). After implantation, the wafer was coated with positive photoresist, exposed, and developed in order to define a cross-shaped Van der Pauw structure. After formation of the DHEM test patterns using dry etching, wafer pieces were processed by rapid thermal anneal (RTA) at 750 ºC, 850 ºC, and 950ºC in nitrogen ambient for 30 seconds. After annealing, samples were subjected to a negative photoresist process in order to open contact windows. After the exposure and development, native oxide was removed from the contact windows and metallic contacts were evaporated. Depth profiles of resistivity, mobility, and carrier concentration were measured by DHEM using an ALPro™ 50 electrical profiling tool. Fig. 1 shows the cross-sectional TEM images of the P ion implanted samples after annealing at (a) 750ºC, (b) 850ºC, and (c) 950ºC. As can be seen in Fig 1(a) the end of range (EOR) defects are located at approximately 26-30 nm from the surface in this sample. The 750ºC RTA process did not adequately resolve these defects. However, it is clear from the TEMs that defects at the original location of the a-Si/c-Si interface decreased gradually when the samples were annealed at increasing RTA temperatures (see Fig. 1(b−c)), when crystallinity of the ion implanted top layer also improved. The depth profiles of active carrier concentration after RTA process are given in Fig.2(a). Three regions can be discussed in these depth profiles. Region 1 is within 15nm of the surface, region 2 is at around 20-30 nm depth, and region 3 is at depths at or larger than 40nm. As can be seen in this figure, higher and higher RTA temperatures result in diffusion of P impurities deeper, and dopant activation at region 3 gets higher and higher as the anneal temperature is increased from 750ºC to 950ºC. As for the region 1, we observe a small decrease in carrier concentration values with higher temperature (from about 3.77E+20 #/cm3 to about 2.95E+20 #/cm3) as the overall active dopant profile becomes more uniform due to diffusion. Figure 2(b) shows the mobility depth profiles of the three samples discussed with reference to Fig. 1 and Fig. 2(a). It is obvious from this figure that the mobility profile is relatively flat within the implantation region (ºC sample dips at a depth in the range of 25-30 nm, where Fig. 1(a) shows extensive EOR defectivity. Therefore, the correlation with deteriorated mobility at that region is excellent. It is also clear from the mobility data that as the annealing temperature is raised to 850ºC and then to 950ºC this dip in mobility disappears, suggesting reduction in defects through higher temperature annealing. Deeper region (>40nm) mobility reduces with increasing temperatures because of increased carrier scattering mechanisms as more of the dopant is activated deeper at the elevated temperatures. Through this work we have demonstrated how DHEM technique can be utilized to correlate electrical and physical data obtained from samples subjected to doping processes. At the present time we are extending this work to ultra shallow junction structures and these results will be presented at the conference. References: Abhijeet Joshi and Bulent Basol, “ALPro System: An Electrical Profiling Tool for Ultra-thin Film Characterization”, 2017 Frontiers of Characterization and Metrology for Nanoelectronics (FCMN), pgs.170-172. Figure 1

A novel Electrochemical Mechanical Planarization (eCMP) process was developed and integrated on the copper plating platform to meet the stringent technical requirements including higher planarization efficiency, higher throughput at lower down force and lower defectivity for the manufacture of devices at 65 nm and beyond technology nodes. In the integrated system, following the electroplating process, the wafer is transferred to the planarization module where the bulk of copper is polished and planarized at a high rate, leaving a thin, planar copper film. It was determined that the resulting planar thin film enables conventional chemical mechanical polishing to clear the remaining copper and barrier with low dishing and erosion. The planarization mechanism of the eCMP process was explained on the basis of electrochemical experimental results.

Electrochemical mechanical deposition (ECMD) is a novel technique that has the ability to deposit planar conductive films on non planar substrate surfaces. This technique involves electrochemical deposition (ECD) while simultaneously polishing the substrate surface. Preferential deposition of the conductor into the cavities on the substrate surface may be achieved through two different mechanisms. The first mechanism is more mechanical in nature and it involves material removal from the top surface. The second mechanism is more chemical in nature, and it involves enhancing the deposition into the cavities where mechanical sweeping does not reach and reducing deposition onto surfaces that are swept. In this study we demonstrate that in an ECMD process, low-pressure mechanical sweeping of the wafer surface during copper plating can establish a differential in the activity of the organic accelerator species between the surface and the cavity regions of the substrate and thus give rise to bottom-up f...

Electrochemical mechanical deposition (ECMD) is a new method that has the ability to deposit planar copper films on nonplanar substrate surfaces. The technique involves electrochemical deposition (ECD) and simultaneous sweeping of the substrate surface with a planarization pad. In this study, we investigated if there were any fundamental differences in the crystallization mechanisms of copper layers grown by the ECD and ECMD techniques. Comparing the variation of the electrical resistivity values over time for films deposited by ECD and ECMD methods and stored at around 18 °C, we found that there were only slight differences in the incubation periods of self-annealing. The activation energies for recrystallization were found to be 0.71 and 0.61 eV for layers grown by the ECD and the ECMD techniques, respectively. The major difference between the ECD and ECMD films was found in the crystalline texture, with ECD layers having a higher degree of (111) preferred orientation compared to the ECMD layers in their as-deposited form. After annealing, the situation reversed, and the ECMD layers displayed a higher (111)/(200) ratio compared to the ECD layers. Differences in texture are believed to result from the mechanical action of the pad on the ECMD copper layers which interfere with and alter the orientation of the growing grains. After high-temperature annealing, ECMD Cu layer microstructure was found to display larger grain size and more fully developed twins indicative of more complete recrystallization.

A novel electrodeposition technique is described for deposition of conductors on non-planar surfaces of substrates in a planar manner. Electrochemical Mechanical Deposition (ECMD) technique involves simultaneous electrochemical deposition and mechanical polishing of the substrate surface. Copper layers deposited by the ECMD process grow preferentially in cavities on the wafer surface yielding flat profiles and much reduced overburden thickness. ECMD technology's potential to reduce cost of interconnect fabrication and some of its enabling features are discussed in this paper.

We examined the effect of deposition of Na on Mo-coated glasses and the Na content of the substrate glass on standard production Cu(In 1− x Ga x )Se 2 (CIGS)-based solar cells fabricated by selenization of Cu-Ga-In precursor thin films. Under optimal conditions, net Na content has a larger effect on the films than does the choice of substrate glass. Device performances improved with modest amounts of added Na on borosilicate glass. Device performances on soda-lime glass were not improved by adding Na. The supply of Na appears to have been adequate from the glass itself. A peak in device performance was found as a function of integrated Na in the CIGS layer as determined by secondary ion mass spectrometry (SIMS). The Na is found primarily in the areas of decreased grain size in the selenized CIGS where Ga is also found. S, deposited with the Na does not end up in the same place as does the Na. Rather, it tends to move toward the surface and accumulate in a buried layer. This is probably due to the reaction process rather than to the microstructure. Oxygen has no apparent effect on Na behavior in the CIGS.

A systematic study was carried out to investigate the distribution of sulfur (S) in CuInSe2 (CIS) and Cu(In,Ga)Se2 (CIGS) absorbers which were exposed to an H2S atmosphere at elevated temperature. Results demonstrated that S diffusion into CIS layers was a strong function of the original stoichiometry of the absorber before sulfurization. Sulfur inclusion into Cu-rich CIS films was much more favorable compared to S diffusion in Cu-poor layers. The sulfur distribution profile was also strongly influenced by the micro-structure of the original CIS and CIGS layers, with sections of the films with smaller grains accommodating more S. Copyright © 2000 John Wiley & Sons, Ltd.

The group of chalcopyrite semiconductors in the Cu(In,Ga)(Se,S) 2 or CIGSS family synthesized by vacuum techniques have been successfully used in the fabrication of high efficiency thin film solar cells. This paper concentrates on a group of low cost, non-vacuum approaches that are highly promising as alternative methods of preparing chalcopyrite absorbers for thin film solar cell applications. Techniques which are based on ‘particle deposition’ fix the metal ratios in a source material containing sub-micron size particles and then transfer this fixed composition onto large area substrates. In this contribution we present data on nano-particle deposition techniques that yielded chalcopyrite absorbers for the fabrication of over 10% efficient solar cells. Mini-modules with over 7% efficiency have also been fabricated using these low cost approaches.

A novel technique was demonstrated for the growth of CuInSe 2 (CIS) thin "lms. The technique used an ink formulation containing sub-micron size particles of Cu}In alloys. A metallic precursor layer was "rst formed by coating this ink onto the substrate by spraying. The precursor "lm was then made to react with Se to form the CIS compound. The morphology of the CIS layers depended on the initial composition of the Cu}In particles as well as the post-deposition treatments. Solar cells were fabricated on CIS absorber layers prepared by this low-cost ink-coating approach and devices with a conversion e$ciency of over 10.5% were demonstrated. ( 2000 Elsevier Science B.V. All rights reserved.

The viability of semiconductor deposition and treatment processes for manufacturing are assessed and critical issues identified for CdTe, Cu(InGa)Se2, thin film silicon and amorphous silicon technologies. The focus is on increasing throughput and decreasing costs. Specific issues include deposition rate, materials utilization, adhesion, uniformity, equipment and process scale-up, compatibility with subsequent processing, module performance and environmental concerns. © 1997 John Wiley & Sons, Ltd.

CuIn(1−x)GaxSe2 (CIGS) thin films with Ga ratio, x, ranging from 0.55 to 0.75 were grown on Mo/glass substrates by the selenization of metallic precursors in a H2Se atmosphere. Without a postdeposition annealing step the films were found to have a highly graded composition that became Ga rich near the absorber/Mo interface. A high‐temperature annealing step promoted diffusion of Ga to the surface region of the films. These absorbers were used to fabricate glass/Mo/CIGS/CdS/ZnO thin‐film solar cells with open‐circuit voltages ranging from 0.4 to 0.74 V and efficiencies approaching 12%. Devices, as well as the absorber layers, were characterized.

Flexible thin film solar cells have many promising applications in space and terrestrial photovoltaic power systems. In this work polycrystalline thin films of copper indium diselenide (CuInSe 2 ) were deposited on flexible metal foil substrates using the selenization technique. In this method E-beam evaporated CuIn precursor layers were reacted with an atmosphere containing H 2 Se gas at around 400°C to obtain CuInSe 2 . Mo, Ti and Al foils were evaluated as possible substrate materials for CuInSe 2 solar cells. Flexible devices of Mo/CuInSe 2 /CdS/ZnO heterojunction structure were fabricated on Mo foil substrates with a conversion efficiency of above 8%.

A novel technique is developed for the deposition of CuInSe2 (CIS) thin films for solar cell applications. The technique uses an ink formulation that contains Cu-In metallic pigments. A precursor layer is first formed coating this ink onto the selected substrate. The precursor film is then reacted with Se to form the CIS compound. Solar cells were fabricated on CIS absorber layers prepared by this low cost ink coating approach and devices with a conversion efficiency of over 9.0% were demonstrated. © 1998 The Electrochemical Society. S1099-0062(98)08-063-8. All rights reserved.

High efficiency solar cells can be fabricated on CdTe films prepared by a wide variety of deposition techniques. Most of these methods yield CdTe layers that need to be subjected to post-deposition treatments before they can be utilized in high efficiency device fabrication. In some cases these treatments can be made an integral part of the film growth process so that a post-deposition step is not needed. This paper discusses the procedures that are commonly used in high efficiency CdTe solar cell fabrication and reports on a newly emerging technique that holds the promise of becoming a high-throughput industrial process for thin film photovoltaic module production.

CIGS is the leading thin film PV material in terms of it capability to yield high efficiency solar cells. Co-evaporation method already yielded solar cells with close to 20% efficiency. Despite this success, however, commercialization of CIGS has not been aggressive. One reason for this is the fact that CIGS is a complex material. The other reason is the difficulty of scaling up this technology while keeping the cost structure competitive. SoloPower has developed a low cost electrodeposition-based CIGS technology for large scale roll-to-roll manufacturing. The substrate is a flexible metallic foil. CIGS absorber layers are formed through annealing and thermal activation of electrodeposited precursor layers. Top and bottom contacts are formed by roll-to-roll sputtering approaches. The technique has excellent ability to control the composition of the deposited layers over large are substrates. After forming a roll of solar cells, devices are cut and then packaged in module structures. Flexible solar cells with an area of over 100 cm2 were fabricated with over 12% efficiency. Over 1 m2 area modules with an efficiency of 10% were also fabricated.

The two-stage process was used to prepare thin films of Cd(Zn)Te and CuInSe2. The technique involves first depositing the elemental components of the compound onto a substrate in the form of thin stacked layers and then reacting these elemental components to obtain a thin film of the desired compound. While CdTe films grown on thin CdS layers have uniform stoichiometries and sharp interfaces with the underlying CdS layers, CdZnTe films deposited onto similar substrates give rise to diffused CdZnTeCdS interfaces because of the reactive nature of zinc. In CuInSe2 processing, the nature of the reacted compound film strongly depends on the nature of the CuIn layers. CdS/CuInSe2 device efficiencies are also influenced by the method of deposition for the CdS window layers.

CuInSe/sub 2/ (CIS) films were grown on glass and metallic foil substrates by the selenization method. Both E-beam evaporation and sputtering techniques were utilized for the preparation of Cu-In precursors and the properties of these layers were studied. Modules with 816 cm/sup 2/ aperture area yielded efficiencies of about 5% and a power output of 4 W. Smaller modules with efficiencies as high as 7.4% were also demonstrated. An efficiency of 9% was obtained for small area solar cells fabricated on flexible metallic foils. >

An approach has been developed for the preparation of Cu-In precursor layers to be used in the selenization technique. In this approach, the surface of the Mo-coated substrate was chemically modified to improve the growth characteristics of the precursors. Selenization of improved precursors yielded stoichiometrically, morphologically, and mechanically superior CuInSe/sub 2/ films which were used to fabricate over 12 % efficient solar cells. It should be noted that although the specific example presented involves Te interfacial layers and precursors obtained by depositing the In layer first, the technique should be applicable to the more commonly used Mo/Cu/In structures and interfacial layers of other materials. >

Cd/sub 1-x/Zn/sub x/Te films of various stoichiometries have been prepared by the two-stage process. This technique involves depositing thin layers of Te, Cd, and Zn onto selected substrates, and then reacting these layers to form the compound film. Cd/sub 1-x/Zn/sub x/Te films of compositions changing from CdTe to ZnTe have been successfully grown by the two-stage technique on glass and ITO-coated glass substrates. Good quality Cd/sub 1-x/Zn/sub x/Te layers need to be deposited on CdS-coated transparent substrates for front-wall solar cell fabrication. This is possible for the case of CdTe layers. Zn concentrations higher than 25 at.% in the absorber layer gave rise to films with poor morphology and a highly diffused Cd/sub 1-x/Zn/sub x/Te/CdS interface. The reason for this behavior is shown to be the exchange reaction between the Zn in the absorber film and the Cd in the CdS window layer. >

Thin film flexible CuInSe/sub 2/ (CIS) solar cells have been fabricated on light-weight and flexible metallic and polymeric substrates. Evaporated Cu-In alloy precursors were selenized in an H/sub 2/Se atmosphere at around 400/spl deg/C to grow the CIS absorber layers. CdS and ZnO window layers were deposited using the chemical bath deposition technique and MOCVD, respectively. The demonstrated active area AM0 conversion efficiency of 9.3%, and the specific power of >1 kW/kg make the polyimide-based light-weight CIS device very attractive for certain space power generation applications where high specific power and mechanical flexibility are desired.

CuInSe2and related I-HI-VI2 compound semiconductors containing Ga and S are important photovoltaic materials with electrical and optical properties that can be tuned for optimum device performance. Polycrystalline thin films of ternary and multinary compounds from the Cu(In,Ga)(Se,S)2family have already yielded laboratory size solar cells with over 15 % efficiency. Large area photovoltaic modules with over 10% efficiency have also been demonstrated using these materials. In this contribution we present a brief review of the CuInSe2 material characteristics which are important to solar cell performance and their correlation with the processing variables. We concentrate on films obtained by the selenization technique. Selenization of Cu-In precursors is an approach that has yielded good quality CuInSe2films which have been used for the fabrication of high efficiency solar cells.

An approach was developed for electrochemical codeposition of In-Se and Ga-Se films with high repeatability and controllable In/Se and Ga/Se molar ratios to prepare precursor layers for copper indium gallium diselenide (CIGS) film formation by two-stage processes. Full potential of complexation was used for the first time by using aqueous electroplating solutions containing complexing agents at alkaline regime. It was found that tartrate and citrate were suitable complexing agents to solubilize In and Ga ions at high pH, respectively. Because no appreciable complexation of Se occurred, Se reduction potential could be independently controlled by the amount of dissolved Se. Use of alkaline solutions also reduced hydrogen bubble generation and related defects.

This report describes a project to develop a high efficiency thin film CuInSe{sub 2} solar cell using a low-cost process. The two-stage process involves depositing the metallic elements of Cu and In on a substrate in the form of stacked layers, and then selenizing this stacked metallic film in an atmosphere containing Se. Early research concentrated on the electrodeposition technique for depositing the Cu and In films on Mo-coated glass substrates. This resulted in small-area cells with around 10% efficiency, indicating that the technique could yield CuInSe{sub 2} films with good electrical and optical properties. The program then involved scaling up the electrodeposition/selenization technique; fixtures for large-area plating were designed and built, but poor adhesion of the CuInSe{sub 2} films to the Mo-coated substrates and the stoichiometric non-uniformities encountered in the large-area films hindered the efficiency of the devices. The latter part of the program explored a new approach to the two-stage process. An evaporation/selenization approach, where the elemental layers were evaporated onto the Mo-coated substrates for selenization. Solar cells have been produced with efficiencies approaching 11% using E-beam evaporated/selenized CuInSe{sub 2} films. 9 refs., 14 figs., 2 tabs.

This report describes a research program to develop a low-cost technique for producing Cd{sub 1-x}Zn{sub x}Te devices for cascade solar cell applications. The technique involves a two-stage process for fabricating such devices with a band gap of about 1.7 eV and a transparent contact layer of low-resistivity ZnTe. In the first stage, thin films of Cd, Zn, and Te are deposited in stacked layers as Cd{sub 1-x}An{sub x}Te. The second stage involves hearing and reacting the layers to form the compound. At first, electrodeposition was used for depositing the layers to successfully fabricate Dc{sub 1-x}Zn{sub x}Te thin-film devices. These films were also intrinsically doped with copper. For the first time, transparent ZnTe films of low resistivity were obtained in a two-stage process; preliminary solar cells using films with low Zn content were demonstrated. A second phase of the project involved growing films with higher Zn content (>15%). Such films were grown on CdS-coated substrates for fabricating devices. The effects of the solar-cell processing steps on the Cd{sub 1-x}Zn{sub x}Te and CdS/Cd{sub 1-x}Zn{sub x}Te interfaces were studied; results showed that the nature of the interface depended on the stoichiometry of the Cd{sub 1-x}Zn{sub x}Te thin film. A sharp interface was observedmore » for the CdS/CdTe structures, but the interface became highly diffused as the Zn content in the absorber layer increased above 15%. The interaction between the CdS window layer and the Cd{sub 1-x}Zn{sub x}Te absorber layer was found to result from an exchange reaction between Zn in the absorber layer and the thin CdS film. 14 refs., 10 figs.« less

Electrochemical mechanical deposition (ECMD) planarizes copper films as they are plated on patterned wafer surfaces. The technique involves electrochemical deposition (ECD) and simultaneous sweeping of the cathode surface with a pad. Pad sweeping gives rise to a mechanically induced current suppression (MICS) phenomenon if plating is performed in electrolytes containing accelerator and suppressor additives as well as Cl - ions. In this work we studied the MICS phenomenon by partially sweeping blanket wafer surfaces with a small pad and investigating effects of the bath chemistry and wafer surface derivatization on the copper growth rates at the swept and unswept regions of the surface. It was found that, at a given suppressor concentration, copper growth rate differential between the two regions was reduced with increasing accelerator concentration in the bath. Derivatization of the wafer surface in an accelerator-containing solution followed by ECMD in a suppressor-containing bath gave the largest growth differential between the swept and unswept surface portions, suggesting high planarization efficiency. Adsorption-desorption kinetics of the organic additives used in this work were obtained under ECD conditions and found to support the proposed mechanism of MICS.

Electrochemical mechanical deposition (ECMD) is a technique that has the ability to deposit planar metal films on nonplanar substrate surfaces with cavities. The method involves electrochemical deposition and simultaneous sweeping of the substrate surface with a planarization pad. Mechanical action of the pad increases suppression at the swept surface and therefore, mechanically induced superfilling of the cavities takes place. In this study we show that the planarization efficiency of the ECMD process for copper deposition is a strong function of the plating chemistry. Electrolytes containing no organic additives or only accelerators do not yield any planarization. Plating baths with only suppressors show low planarization capability, whereas those containing both suppressors and accelerators yield the highest planarization efficiency. Soaking the wafer surface in an accelerator-containing solution before the ECMD process step increases the planarization efficiency significantly. The presence of levelers in the plating electrolyte is detrimental to planarization efficiency of ECMD. High-acid copper plating solutions display higher planarization capability than low-acid electrolytes.

Electrochemical mechanical deposition (ECMD) is a new technique that has the ability to deposit planar copper films on nonplanar substrate surfaces. This technique involves electrochemical deposition and simultaneous sweeping of the substrate surface with a planarization pad. In this study we show that planarization of low-aspect-ratio features on a wafer surface by ECMD is due to a newly identified mechanically induced superfilling phenomenon. Sweeping of the top surface of the wafer at preset intervals establishes a transient differential in the surface coverage of organic additives at the top surface and the cavity regions, preferentially increasing the current flow into the cavities. Planarization decreases as the time interval between sweeps increases. Increase in the deposition rate of copper into the low-aspect-ratio features results in an associated decrease of deposition onto the top surface under galvanostatic conditions. A model that invokes surface coverage transients of accelerator species is offered to explain the experimental results.

A novel technique is developed for the deposition of CuInSe2 (CIS) thin films for solar cell applications. The technique uses an ink formulation that contains Cu-In metallic pigments. A precursor layer is first formed coating this ink onto the selected substrate. The precursor film is then reacted with Se to form the CIS compound. Solar cells were fabricated on CIS absorber layers prepared by this low cost ink coating approach and devices with a conversion efficiency of over 9.0% were demonstrated. © 1998 The Electrochemical Society. S1099-0062(98)08-063-8. All rights reserved.

A two-stage process was used to prepare thin films of chalcopyrites such as CuInSe2 and CuIn1−xGaxSe2. This process involves reacting the previously electrodeposited stacked metal layers with a chalcogenide atmosphere to obtain single-phase chalcopyrite material. Efficient solar cells of the type CuInSe2/CdS were fabricated on films obtained by this technique. Results reported in this paper demonstrate the promise of the two-stage process for low cost manufacturing of thin film solar cells.

Cd1−x Zn x Te films of various stoichiometries have been prepared by the two‐stage process. The technique involves sequentially depositing thin layers of Cd, Zn, and Te on a substrate and reacting these elemental layers to form the compound. Both electrodeposition and evaporation techniques have been used in this work to deposit the elemental films.Properties of the electroplated elemental films, as well as the structural, optical and electrical characteristics of the reacted compounds, have been studied. Transparent ZnTefilms of low resistivity have been obtained. Cd1−x Zn x Te/CdS solar cells using films processed by the two‐stage technique are demonstrated.

In2O3: Sn films were prepared by an activated reactive evaporation technique developed for this purpose. The films were characterized by transmission electron microscopy, electron diffraction, electrical resistivity and measurements of transmittance as a function of wavelength. The electrical resistivity is found to be strongly dependent on process parameters such as the tin content and the deposition temperature. In contrast, the transmittance is found to be only weakly dependent on various process parameters. Under optimum conditions, films with an electrical resistivity of 7 × 10−5 Ω cm with an integrated (0.4–1.2 μ) transmittance of over 90% were obtained.

A two-stage process was used to prepare polycrystalline thin films of CuInSe2 for solar cell applications. The technique involves first depositing thin layers of copper and indium on a substrate and then selenizing this metallic stack to form CuInSe2. Both electron-beam evaporation and evaporation from resistively heated boats were used to deposit the copper and indium films. Selenization was carried out in an H2Se atmosphere at 400 °C. CuInSe2 films obtained from uniformly deposited metallic layers were found to be of chalcopyrite phase. Heterojunction solar cells with efficiencies close to 11% have been fabricated on these films.

A simple two-stage process is utilized to prepare ZnTe thin films. The technique involves electrodeposition of tellurium and zinc stacked layers out of aqueous electrolytes and reaction of them in an inert atmosphere. The resulting films will be used in cascade solar cell structures.

Thin films of cuprous sulphide (Cu2S) have been deposited for the first time by a novel Activated Reactive Evaporation (ARE) technique. These films have been deposited as a function of various deposition conditions such as partial pressure of hydrogen sulphide gas, substrate temperature and copper evaporation rate. The microstructure of the films have been characterized by optical microscopy, transmission electron microscopy and electron diffraction. Electrical and optical characterization has also been carried out. Films deposited using, a H2S partial pressure in the range from 10−2 to 8 × 10−4Torr. a substrate temperature at or near room temperature and a copper evaporation rate of about 200 A/min, were found to consist of pure chalcocite (Cu2S). Electrical and optical measurements of the pure Cu2S films indicated that these films were p-type with carrier concentrations of 1–7 × 1020/cm3 and typical mobility values of 1–3 cm2/V s. Mobilities as high as 8 cm2/v s were measured on some samples. The optical determination of the band gap gave a value of Eg ≈ 1.2 eV. Preliminary investigation of the Cu2S/CdS heterojunctions were also carried out usin ARE deposited Cu2S films on CdS films prepared by direct evaporation.

Efficient electroplated CdS/CdTe solar cells can be fabricated by heat treating and type‐converting the n‐CdTe films deposited on CdS layers. In this paper, various mechanisms which may give rise to the conversion of electroplated CdTe films from n to p type are investigated. It is concluded that Cd‐vacancy generation is the main mechanism of type conversion. Possible effects of oxygen on this mechanism are also discussed. Evaporated Au contacts to electroplated p‐CdTe films were studied. It was found that the Au contacts depleted the excess Te present on the surface of Br2‐methanol etched p‐CdTe films. Oxygen was found to affect the electrical characteristics of such contacts.

The capacitance of the Schottky barrier devices formed on high resistivity n-type CdTe films is analyzed. CdTe films are obtained by an electrodeposition method. Deviation in the capacitance from the expected behavior is explained using a model that takes into account the effect of a large density of deep traps in the material. Results are compared with the values reported previously for CdTe prepared by other techniques. A single dominant trap level is observed and identified as an electron trap which is 0.56 eV below the bottom of the conduction band edge. The capture cross section σ and the density of those traps are determined to be 7×10 −14 cm 2 and (1.7−3)×10 16 cm −3 respectively.

Electroplated CdS/p-Hg1−x Cdx Te (MCT) thin-film solar cells with (1 - x) are evaluated and compared with electroplated CdS/p-CdTe devices. It is shown that the series resistance limitations commonly observed in CdS/p-CdTe devices can be appreciably reduced if p-CdTe is replaced by p-MCT. This is due to the lower resistivities attainable in p-MCT thin films which in turn reduce both bulk and contact resistances. The possiblity of bandgap control in MCT makes it an important candidate material for the production of high-efficiency tandem cells.