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A latest demonstration of superconductor oscillator/counter A/D Converter up through twelve Giga-Sample per second (12 GS/s) with 3 effective bits of signal-to-noise ratio at that sample rate is presented along with analysis of its performance. This A/D Converter incorporates a new technique for defining the aperture using inter-Josephson transmission line single-flux-quantum repulsion.

A recent demonstration of a Multiply-Accumulate (MAC) unit, which is the core of digital signal processor that implements programmable band-pass signal filtering, is presented. The design approach and risks associated with fringe field magnetic coupling between bias and signal lines are discussed.

Research ivolving the application of first-in, first-out (FIFO) buffers to circular shift registers, serial memory and data re-clocking is described and discussed.

Challenges and solutions having to do with designing high-performance superconductor processors are discussed.

A second iteration Flux-1 chip is described. It will be tested in Aug/Sep 2002.

Research is presented concerning the use of LTS rapid single-flux quantum techniques as the basis for the design and construction of a single-chip microprocessor. Dual-processor modules using both chips are discussed.

The preliminary design of the COOL-0 rapid single-flux-quantum (RSFQ) subsystem for petaflop computers is described. COOL-0 is based on 0.8-micrometer RSFQ technology, superconducting processing elements at clock frequencies of up to 100 GHz, pipelined cryo-memory with 30 ps cycle time and interprocessor network with a bandwidth of 30 Gbps per channel. It would occupy a space of 0.5 cubic meter and consume power as low as 250 watts at helium temperature.

A design for parallel pipelined carry-lookahead Kogge-stone 32- and 64-bit integer adders with the traditional concurrent flow timing scheme is presented. The objective was to go through all the design stages of a large Rapid Single Flux Quantum Circuit (RSFQ), namely, a parallel pipelined adder. Results of its gate-level logical simulation using a VHDL model, with parameters reduced from the physical-level simulation of RSFQ cells are presented.

A new rapid single-flux-quantum (RSFQ) microprocessor architecture was proposed. The new architecture has D2 cells that function as the data processing pipeline, an all-RSFQ self-reset decoder ideal for pipelined implementation and a 16-bit pipelined register block. The general-purpose RSFQ microprocessor has a predicted command cycle time of about 1 ns and implements the command set for 16-bit data words processed in nibble-serial method.

A general-purpose high-performance microprocessor architecture developed specifically for rapid single flux quantum (RSFQ) circuits allows design of dc-powered digital circuits timed by locally generated clock pulses with frequencies in excess of 100 GHz. It also allows faster memory storage and allows an increase in data path width. This RSFQ microprocessor could be easily fabricated using a 16-bit Josephson junction computer system.

Research is discussed that enables floorplanning of random logic chips to be implemented in future Josephson junction technologies.

We have developed a low Jc (100-1000 A/cm2) submicrometer Nb integrated circuit fabrication process for SQUID based quantum computing applications. The baseline process consists of 7 masking steps including Pd-Au resistor, Nb/A1-A1Ox/Nb trilayer, two Nb wiring layers and two sputtered SiO2 dielectric layers. We have also fabricated wafers with an Nb ground plane. Using deep-UV lithography, inductively coupled plasma etch tools, and self-aligned lift-off for device definition, we routinely achieve micrometer lines and spaces with 400 nm minimum junction dimensions. Room temperature testing is used to select wafers in process and junction annealing has been calibrated for trimming current density. We will describe the process which has been used to produce circuits with over 100 junctions. [ABSTRACT FROM AUTHOR]

Describes the design and implementation of a single-chip microprocessor based on rapid single flux quantum technology. Design objectives; Microarchitecture; Critical path timing; Validation and testing of the superconductor processor prototype.

Rapid Single-Flux-Quantum (RSFQ) logic, based on the representation of digital bits by single quanta of magnetic flux in superconducting loops, may combine severalhundred-GHz speed with extremely low power dissipation (close to 10[sup -18] Joule/bit) and very simple fabrication technology. The drawbacks of this technology include the necessity of deep (liquid-helium-level) cooling of RSFQ circuits and the rudimentary level of the currently available fabrication and testing facilities. The objective of this paper is to review RSFQ device physics and also discuss in brief the prospects of future development of this technology in the light of the tradeoff between its advantages and handicaps. [ABSTRACT FROM AUTHOR]

Discusses the preliminary design of a rapid single-flux-quantum (RSFQ) integrated circuit for general purpose computers with petaflops-scale performance. Implementation of superconductor processing elements; Multithreading and context prefetching; Physical structures and estimated parameters.