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High-resistivity polycrystalline silicon (HRPS) wafers are explored as a novel low-cost and low-loss substrate in Wafer-Level Chip-Size Packaging (WLCSP) for RF applications. The WLCSP solution we demonstrate is based on adhesive bonding of a HRPS wafer to a silicon wafer with active devices. After bonding, the IC wafer is thinned below 50 µm and selectively removed to expose its front-side contact pads. The HRPS wafer serves as a mechanical carrier, thermal spreader and vertical spacer in which vias are etched by DRIE to reach desired pads on the IC wafer. Then after a seed layer sputtering, a 5-10 µm Cu layer is plated on both wafer sides and patterned providing a back-side ground plane and large, front-side RF passives. Due to HRPS electrical properties, no dielectric isolation layer is required inside vias, simplifying the front-side processing. Solder bumping on the substrate backside and singulation by dicing complete the processing. The presented concept enables integration of large RF passives with a spacing of >150 µm to the conductive silicon substrate containing the circuitry, while providing mechanical stability, reducing form factor and avoiding any additional RF loss. Antenna performance comparable to glass substrates and high quality factors for large spiral inductors (Q=11 at 1 GHz; 34 nH) are demonstrated. The HRPS substrates have high dielectric constant, low RF loss, high thermal conductivity, perfect thermal matching, and processing similar to the single-crystalline silicon., Fundação para a Ciência e a Tecnologia (FCT) – SFRH/BD/4717/2001, POCTI/ESSE/38469/2001, FEDER., Comunidade Europeia (CE) – (project Blue Whale IST – 2000 – 3006).

This paper reports on design and fabrication options of an integrated folded shorted-patch chip-size antenna for applications in short-range wireless microsystems. The antenna is built using a stack of two adhesively bonded wafers with patterned metallization and through-wafer electrical interconnects. Different fabrication options based on via formation in glass and/or high-resistivity silicon substrates using excimer laser ablation or powder blasting are analyzed., Fundação para a Ciência e Tecnologia (FCT) (SFRH/BD/4717/2001, POCTI/ESE/38468/2001, FEDER), and EC (project Blue Whale IST-2000-10036).

We report on design and fabrication of a folded-patch chip-size antenna for operation at 5.7 GHz and use in short-range wireless communications. Application of wafer-level chip-scale packaging (WLCSP) techniques like adhesive wafer bonding and through-wafer electrical via formation, combined with the selected antenna type allows on-chip integration and is the main novelty of our design work. This antenna, built on two stacked substrates, allows size reduction down to 4.5x4x1 mm3 and has projected efficiency of 66%., Fundação para a Ciência e Tecnologia (FCT) (SFRH/BD/4717/2001, POCTI/ESE/38468/2001, FEDER), and by EC (project Blue Whale IST-2000-10036).

This paper reports on fabrication and design considerations of an integrated folded shortedpatch chip-size antenna for applications in short-range wireless microsystems and operating frequency of 5.7 GHz. Antenna fabrication is based on wafer-level chip-scale packaging (WLCSP) techniques and consists of two adhesively bonded glass wafers with patterned metallization and through-wafer electrical interconnects. Two different fabrication options based on via formation in glass substrates using excimer laser ablation or powder blasting are presented., Fundação para a Ciência e Tecnologia (FCT) - (POCTI/ESE/38468/2001, SFRH/BD/4717/2001), EU (IST-2000-10036).

The measured S-parameters of a coplanar waveguide (CPW) propagating the dominant mode were used to obtain the electrical permittivity and the dielectric loss tangent of three different glass wafers: non-alkaline Schott AF45, Corning Pyrex #7740 and Hoya SD-2. These properties were obtained up to 10 GHz. The obtained values were used together with the CPW model in ADS to obtain the simulated S-parameters for the used CPW cell. The obtained results shows good agreement between simulated and measured data., Fundação para a Ciência e Tecnologia (FCT) - (POCTI/ESE/38468/2001).

We report on design, fabrication and characterization of chip-size antennas for operation at 5.7 GHz and use in wireless sensor networks. Application of wafer-level chipscale packaging (WLCSP) techniques like adhesive wafer bonding and through-wafer electrical via formation, combined with the selected antenna types (patch and folded patch) allows on-chip integration and is the main novelty of our work. A short-range wireless link between two systems both equipped with an 8x8 mm2 patch antenna (measured characteristics: 5.705 GHz central frequency, 90 MHz bandwidth @ -10 dB, 0.3 dB gain, 18% efficiency) realized on a high-resistivity silicon (HRS) substrate is demonstrated. A folded-patch antenna built on two stacked glass substrates allows size reduction down to 4.5x4x1 mm3 and has a projected efficiency of 60%., Fundação para a Ciência e Tecnologia (FCT), project (SFRH/BD/4717/2001 and POCTI/ESE/38468/2001).

This paper presents the design and characterization of a patch antenna built on lossy substrates compatible with integrated circuits fabrication. Two different substrates were used for antenna implementation: high-resistivity silicon (HRS) and Corning Pyrex #7740 glass. The antenna prototypes were built to operate close to the 5 GHz ISM band where applications like HIPERLAN and IEEE802.11a are standardized. They operate at a center frequency of 5.705 GHz (HRS) and 5.995 GHz (Pyrex). The studied parameters were: substrate thickness, substrate losses, oxide thickness, metal conductivity and thickness. The antenna on HRS uses an area of 8 mm2, providing a 90 MHz bandwidth and ~0.3 dBi of gain. On a glass substrate, the antenna uses 12 mm2, provides 100 MHz bandwidth and ~3 dBi of gain., Fundação para a Ciência e Tecnologia (FCT), project (SFRH/BD/4717/2001 and POCTI/ESE/38468/2001)

We report on design and characterization of chip-size antennas for operation at 6 GHz and use in wireless microsystems. Use of a glass substrate and application of wafer-level chipscale packaging (WLCSP) techniques like adhesive wafer bonding and through-wafer electrical via formation, combined with the selected antenna type allows on-chip integration and is the main issue of our work. A short-range wireless link between two systems both equipped with a 11.7x12.4 mm2 patch antenna (measured characteristics: 6 GHz central frequency, 100 MHz bandwidth @ -10 dB, 3 dB gain, 51% efficiency) realized on a Corning Pyrex #7740 glass substrate is demonstrated., Fundação para a Ciência e Tecnologia (FCT), project (SFRH/BD/4717/2001 and POCTI/ESE/38468/2001)

We report on the design of a novel, very small dualband antenna having double-folded structure and suitable for onchip integration in wireless sensor network nodes. The antenna operates simultaneously at 2.4 GHz and 5.7 GHz with a -10 dB return-loss bandwidth of 50 MHz and 170 MHz, respectively. A prototype fabricated on a 4003 RogersTM substrate (dielectric permittivity of 3.38) has dimensions of 6x8.5 mm2., Fundação para a Ciência e Tecnologia (FCT) (SFRH/BD/4717/ 2001, POCTI/ESE/38468/2001, FEDER).

We report on the use of slots for size reduction and tuning of folded patch antennas operating in the 5-6 GHz ISM band, with intended application in short-range wireless communications. Varying the slot length modifies the antenna electrical length, thus providing a new degree of freedom to control the antenna operating properties, and is the main novelty of our work. This technique was used for antenna tuning, input impedance control, and, very important, for antenna size reduction. Keeping the operating frequency at 5.7 GHz, application of slots allows an antenna size reduction close to 30%. Keeping the antenna dimensions constant, application of slots allows its tuning from 5.7 GHz down to 4.8 GHz and is potentially suitable for dynamic antenna reconfiguration., Fundação para a Ciência e Tecnologia (FCT) (SFRH/BD/4717/ 2001, POCTI/ESE/38468/2001, FEDER).