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A mixed-signal binarized neural network (BNN) processor for the MNIST image classification is demonstrated based on analogue circuit networks. BNN algorithm for training neural networks with binary weights and activations reduces power consumption and memory size. This algorithm is a design to perform core operations of multi-layer perceptron (MLP) to reduce complexity and power consumption using analogue circuits. The mixed-signal BNN processor employs a current mirror neuron to perform multiply-and-accumulate (MAC) operations and sign activation functions. The near-threshold current mirror neuron that computes the key operations of the BNN algorithm is used to achieve low power consumption. The design occupies 0.065 mm2 in 28-nm CMOS with 560B of on-chip SRAM. The 28-nm CMOS test-chip achieves energy efficiency of 24.1 TOPS/W and 94% accuracy on the MNIST image classification. This design with binary weights and activations exhibits only 5% degradation in accuracy compared with the models with floating-point precision. [ABSTRACT FROM AUTHOR]

This letter presents an 11 b 200 MS/s 28 nm CMOS 2b/cycle successive‐approximation register (SAR) analogue‐to‐digital converter (ADC). The offset calibration technique is proposed to reduce the comparator offset mismatch that degrades the linearity of the high‐resolution 2b/cycle SAR ADC. The offset mismatch is reduced to within 0.25 least significant bit (LSB) by generating a compensation voltage from capacitor‐resistor (C‐R) hybrid digital‐to‐analogue converters (DACs). The prototype ADC implemented in a 28‐nm CMOS process demonstrates measured differential and integral non‐linearities within 0.6 LSB and 1.73 LSB at 11 b resolution, respectively. The measured signal‐to‐noise‐and‐distortion ratio (SNDR) and spurious‐free dynamic range (SFDR) are 50.9 dB and 66.2 dB at Nyquist, respectively. The prototype ADC occupies an active die area of 0.115 mm2 and consumes 3.98 mW at a 1.1‐V supply voltage.This letter presents an 11 b 200 MS/s 28‐nm CMOS 2b/cycle successive‐approximation register (SAR) analogue‐to‐digital converter (ADC). The proposed calibration technique reduces the comparator offset mismatch to within 0.25 LSB at 11 b resolution, enabling the implementation of high‐resolution 2b/cycle SAR ADC. [ABSTRACT FROM AUTHOR]

A single stage monolithic millimeter wave optical receiver circuit was designed and fabricated using a metal-semiconductor-metal (MSM) photodetector and a pSeudomorphic Modulation Doped Field Effect Transistors (SMODFET) on a GaAs substrate for possible applications in chip-to-chip and free space communications. The MSM photodetector and the SMODFET epitaxial material were grown by molecular beam epitaxy (MBE). Device isolation was achieved using an epitaxially grown buffer between the MSM detector layers and SMODFET. The photodetector was designed for maximum absorption at optical wavelength of 770 nm light and the SMODFET impedance matching network was optimized for 44 GHz. The monolithic millimeter wave optical receiver circuit achieved 3 dB gain over a photodetector at 39 GHz, which was the limit of the measurement system. TOUCHSTONE model of the circuit indicated 6.6 dB gain over the photodetector and 5.7 dB total gain including the insertion loss of the photodetector at 44 GHz.

Metal-semiconductor-metal photodetectors have been created which are made of an Al(sub x)Ga(sub 1-x)As cap layer, a thin GaAs absorption layers and a buried Bragg reflector stack. They have submicron spaced interdigitated Schottky barrier fingers. They are for use in monolithic integrated optical receiver circuits which can detect millimeter-wave modulation They have a high-frequency response, over 39 GHz.

A small-signal equivalent circuit model for III-V nitride modulation doped field effect transistors (MODFETs) was developed through parasitic extractions. Because of the high contact resistance of current III-V nitride MODFETs, a special technique was needed for extracting the Z-parasitic elements. The highly resistive source and drain contacts were modeled as transmission lines and each element in the transmission line was determined from the Z-parasitic measurements.

A 13.5-mW 10-Gb/s four-level pulse-amplitude modulation (4-PAM) serial link transmitter is presented. To improve the power efficiency, a voltage-mode 4-PAM driver is proposed. It consists of voltage-scaled pull-up and pull-down networks, instead of conventional current switching networks. Not employing a tail current source, the proposed 4-PAM driver achieves the higher output voltage swing and lower power dissipation than conventional 4-PAM drivers. As a result, the proposed 4-PAM transmitter implemented in a 0.13- \mu\m CMOS process achieved 10-Gb/s data rate with only 13.5-mW power dissipation. [ABSTRACT FROM AUTHOR]