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The article discusses the performance of microprocessors has been characterized in terms of word size and operating frequency. The author cites that 100 watts or more chip has forced central processing unit designers to rethink the standard approach of increasing the clock speed to improve performance.

The article discusses the trends of memory systems for the next generation and the challenges faced by memory system designers. Dynamic Random Access Memory (DRAM) vendors offer faster memory architectures, denser chips and system interfaces which can boost system performance while allowing users to add memory systems. Third generation double-data-rate synchronous DRAMs or DDR3 DRAMs are emerging with 400 to 800 Megahertz clock speed.

The article reports on the development of Xilinx Inc.'s forthcoming Virtex 5 generation of field programmable gate array in the U.S. Semiconductor companies are shifting to 65-nanometer design rules which predict exceptional logic density and performance. The design rules showed an edge in process technology, circuit design, physical lay-out and software methodologies and equipped with engineering talent.

Information on activities that happened during the Multicore Expo in Santa Clara, California. The exhibition featured microprocessors that can process 31 gigabit per second. Conference presentations discussed developments in multicore and multithreaded architectures and highly parallel-processing arrays.

This article discusses advances in Not And (NAND) flash memories that promise to raise performance and semiconductor storage capacity. These memories are in demand for storage of image files in MPEG-4 video cameras and digital cameras, as well as for storage of digital audio and digital video in multimedia players. Single-bit-per-cell (SLC) and two-bit-per-cell are two types of NAND flash devices. Samsung and Toshiba offer high-capacity monolithic flash chips that use multilevel cell schemes. Advances are in the area of circuit architecture, process technology, and cell structures.

The article features on the new designs in field programmable gate array (FPGA) architecture developed and distributed by Actel Corp., Altera Corp., Amtel Systems Corp., Lattice Semiconductor Corp., QuickLogic Corp., Xilinx Inc., GiDEL Ltd., Nallatech, SBS Technologies Inc., and VMetro Inc..

The article discusses the concept of complementary metal oxide semiconductor (CMOS)-based image sensors. CMOS-based image sensors are more economical and perform better than charge-coupled-device sensors for imaging devices with resolutions ranging from sub-video graphics array to 8 megapixels. The sensors leverage the process scaling of CMOS technology and the ability to integrate logic functions particularly image processors and analog-to-digital converters. Advancement in lithography and pixel design allow for further scaling, enabling designers to craft devices with even higher resolutions. The Foveon Corp. has come up with an unusual approach in creating a CMOS imager by using three layers of pixels in the silicon. Sensors with 5-megapixel resolution are in demand among consumers for mainstream differential scanning calorimetry applications.

The article presents information on low-cost programmable gate arrays. Now nothing will impede the field-programmable gate array's (FPGA) march into scores of volume applications. New architectures both lower the cost and improve functionality, enabling them to cost-effectively compete with application specific integrated circuits (ASICs). Smaller process geometries that shrink chip size go a long way toward reducing cost. But size isn't the only factor in the cost equation. Also driving the use of programmable devices is the shorter product life of many mass-market products. With ASICs, designers typically must allow for manufacturing cycle times of a month or more. Then there are the nonrecurring-engineering (NRE) costs. Programmable logic devices combat all of the above issues. These off-the-shelf parts have no significant NRE charges. If the system is designed properly, they can be updated in the field to correct system flaws or add new features. The per-chip costs might be higher than those of an ASIC, but after considering these other factors, FPGAs become a more cost-effective solution. To further the trend, all companies that offer FPGAs have developed families of low-cost devices that now target mass-market applications.

Focuses on the deeper relationship between designers and manufacturing partners to battle escalating chip design costs. Information that electronic-design-automation (EDA) tool suppliers are forming closer relationships with foundries; Integration of large semiconductor companies; Disaggregation of the typical semiconductor supplier triggered the emergence of independent EDA tool vendors like Cadence Design Systems Inc., Mentor Graphics, and Synopsys; Creation of wafer foundries.

This article presents an outlook for trends in broadband network technology: "Content continues to accelerate as networks run faster and larger amounts of storage get shoehorned into ever smaller products...Driving the need for more storage are today’s lightning-speed Internet connections...Within the home, it’s becoming more common to have wired and wireless Ethernet networks that move data at rates from a few megabits per second to 1 Gbit/s. Give it a few more years, and they will be ubiquitous...Thanks to either Wi-Fi or wired Ethernet connections, the Roku Soundbridge music-player systems can connect to a stereo or powered speakers and play content from a PC or other network source...In the automotive space, we already have an abundant number of car-installed DVD playback systems to entertain passengers...Also getting updated is the stereo in the cabin."

The article reports that the dynamic random-access memory (DRAM) market has fragmented into a plethora of options at both the chip and the memory-module level. During its 30-plus years, the venerable DRAM has undergone a series of facelifts to boost density and performance. And the nipping and tucking is not over, with system designers demanding more performance and bits per chip. Today, about a half-dozen basic DRAM types are available to meet various performance needs. The largest category, the mainstream DRAM, includes the older synchronous DRAM (SDRAM), double-data-rate SDRAM (DDR1 SDRAM), and the second-generation DDR (DDR2 SDRAM). These devices are used by personal computers, workstations, and server manufacturers, as well as in many consumer, industrial, and networking applications. The first-generation DDR DRAM turns four years old this year. New designs are moving rapidly to the next-generation DDR2 memories, though, thanks to their higher performance and lower power. Lower operating voltage and the shorter access times, among other reasons, explain why DDR2 memories are more attractive for high-performance systems.

This article looks into the design secrets behind the next generation of gaming systems. With central processing units running at several gigahertz plus a high-performance video card or two, personal computer gaming has become as lifelike as its console-based competition. The gaming systems examined include the Sony PlayStation 2, Microsoft X-Box, XaviX game systems, the Nintendo DS dual-screen handheld system, among others. Cellular telephones have also become another platform by offering built-in and downloadable games.

This article focuses on application specific integrated circuits (ASIC). The rules of the ASIC game are changing as the cost to fabricate a custom solution creeps past the million-dollar mark. And, new rules are emerging due to the shorter market life of the end system and the continuous need to upgrade or update a product's features. Device cost is always a key factor for filed programmable gate arrays (FPGAs), especially those used in the final version of a product. The high-density, resource-rich, top-of-the-line FPGAs tend to cost several hundred dollars to over a $1000 apiece, even in moderate volume. INSETS: FPGAs ENTER NEW DESIGN TERRITORY;STRUCTURED ASICs COMPETE WITH, AND COMPLEMENT, FPGAs.

Programmable logic has become a vital part of design. This article explores the options for complex programmable logic devices and field programmable gate arrays for optimizing system performance in electronic design. Details are presented on input and output issues, capacity and memory options, hard and soft options for embedded processors, and design tools to pull the design together.

Over the last half decade, a new class of configurable application specific integrated circuits (ASIC) has made inroads by bridging the performance and cost gap between designs based on full custom ASIC and high density field programmable gate arrays (FPGA). Known as platform and structured ASICs, these system-on-a-chip solutions are some of the best aspects of custom ASIC and FPGA. As a result, designers have a quick time-to-market option that features lower development costs than ASIC and higher performance and often lower unit costs that FPGAs.

Focuses on the role of microprocessors on the computer industry in the U.S. Capability to perform billions of operations per second; Efforts to develop microprocessors with greater computational throughput; Companies demonstrating adaptive computer architecture.

Focuses on the low-cost dedicated and programmable videoengines delivering the performance and flexibility needed to handlethe plethora of standards that decode or encode the expanding videocapabilities within the consumer and business applications. Disadvantage of several high-end general-purpose central processingunits; Advantage of dual datapaths in thevery-long-instruction-word core of Texas Instrument's TMS320C6211;Requirement of various video algorithms.

Explores semiconductor static random access memories (SRAM) that meet high-performance demands of switching, routing and server applications. Zero bus turnaround SRAM; Double data transfer rate SRAM; Quad-data-rate SRAM. INSETS: 1. The two master clocks, K and K#, control the timing for...;2. Fujitsu's fast-column DRAM overlaps the command and...;Modeling Next-Generation SRAMs;DIFFERENCES BETWEEN TWO-WORD AND FOUR-WORD BURST QDR SRAMS

Features the Bus Doctor electronic system design from Data Transit. Basic sections of the Bus Doctor hardware; Inclusions in the first software release for the Bus Doctor; Performance capabilities of Bus Doctor.

Features California Micro Devices Corp.'s EZTerm, a nonlinear active termination building block. Product specifications; Applications; Price; Purchase and licensing agreements offered; Contact information.

Discusses the design of field-programmable gate arrays (FPGA) from QuickLogic Corp. that combine multiple serial interfaces and logic. Configuration of the dual-ported random access memory to appear as multiple asynchronous first-in, first-out buffers; Direct circuit balancing; Division of the clock grid; Timing and interface flexibility.

Reports that high-density field programmable gate arrays (FPGA) take on system ASIC features and performance levels. Additional logic for clocks; Configuration of the Nios central processing unit soft core; ORCA FPGA technology crafted by Lucent Technologies Inc.; System solution on a chip from Triscend Corp. INSETS: Synthesis Tools Come Of Age For FPGAs.;Extending The Boundaries Of Digital Systems..

Comments on the impact of advances in the creation and standardization of intellectual property (IP) for allowing systems on a chip designers to better assemble complex integrated circuit solutions. Variety of forms in which IP building blocks are available; Strategies for solving legacy problems. INSET: When Analog And Digital Must Meet: Easing the Integration Of....

Reports on Chameleon Systems' development of its CS2000 line of reconfigurable communications processors. Reduction of programming time; Integration of a proprietary reconfigurable processing fabric; Memory bus connection through an external-memory controller; Contact information.

Focuses on optimized processor blocks which eliminate the risks of reduced instruction set computers (DSP) for system-on-a-chip designs. Central processing units; Digital signal processing (DSP) cores; Bus interface specification; Configuration options; List of suppliers of RISC and DSP cores.

Focuses on erasable programmable read-only memory computer storage devices. Features of such computer storage devices; Available versions; Functionality and applications.

Focuses on Silicon Magic Corp.'s DVine architecture which provides a modular, scalable microprocessor that leverages embedded dynamic random access memory (DRAM). Functionality and applications of the microprocessor; Main modular sections comprising the DVine architecture; Price and availability of such products.

Reveals the features of content-addressable memories (CAM) which enable them to speed up computer network traffic. Includes extra transistors; Record-count feature which can help an application determine whether a table is full; List of CAM manufacturers; Difficulties of future embedded-systems design; CAM emulation. INSET: Manufacturers of content-addressable memories..

Reports on the technologies being developed by high technology firms in the United States to achieve higher Internet bandwidth. Potentials of the wavelength division multiplexing (WDM) and the dense WDM; Lucent Technologies and Bell Laboratories' research on optimized fiber-optic fibers; Development of higher-speed laser diodes.

Discusses the use of highly parallel architectures in accelerating digital signal processing (DSP) chip or high-performance central processing unit (CPU). Overview on the capabilities of the highest performance DSP chips; Background on various processors that are capable of DSP-like functions; Sample applications.

Focuses on the applications of the storage device NOR-style flash memory in the semiconductor industry. Impact of process technology developments on the performance and density of flash memories; Effects of using flash memories in small portable devices on packaging and power supply; Directory of manufactures of NOR-style flash memories.

Assesses the role of Layer-3 switches, devices that combine the Layer-2 functions of the network switch and the Layer-3 functions of the router for Internet applications. Allayer Technologies' AL300 network switch chip; Lower per-port costs; Chip features.

Explores the flexible, reconfigurable multiplier block as an embedded function for field programmable gate arrays (FPGA). Functions of the multiplier-block concept; Dedicated blocks of memory or application-specific logic; Networking and data communications as one of FPGA applications. INSET: System-On-A-Chip Designs Also Can Leverage Programmable Tec....

Reports the creation of ProASIC 500K family of flash-based field programmable gate arrays (FPGA) by Actel. Specifications and advantages of the ProASIC FPGA series; Relevance of finegrained logic-cell architecture in the flexibility of the 500K series; Availability and price of ProASIC chips.

Focuses on the architecture of Synchronous Dynamic Random Access Memory (DRARM) and Direct Rambus DRAM (RDRAM), competing memory cards for microcomputers. Advantages of enhanced Direct RDRAM; Factors affecting delay in readying RDRAM motherboard chips sets; Enhancement of memory systems; Optimization of system performance and cost with DRAM systems.

Highlights the Delta39K family of complex programmable logic devices (CPLD) from Cypress Semiconductor. Basic macrocell architecture of the logic devices; On-chip configuration RAM in the logic devices; Optional multichip module approach; Operation power supply options offered by the devices.

Reports on the set-top box (STB) enhancement through high-speed RISC CPUs and programmable media processors. Transformation into an interactive entertainment center; Expansion of the STB market through the OpenCable initiative; Advanced graphics, telephony capability, and handling banking operations; Two-chip logic solution.

Focuses on the increased densities of NAND-style flash-memory devices. Basic architectural option for electrically erasable programmable memories; Chance for designers to turn standard random-access flash memories into disk-drive-like storage.

Focuses on the integration of flash memory into microcontrollers and embedded processors design. Advantages of flash memory in the electronic design; Versions of processors or application specific integrated circuits with DSP cores; Function of electrically erasable programmable ROM; Manufacturing process of flash memory.

Looks at three papers presented during the 1999 IEEE International Solid-State Circuits Conference focusing on advances in processor speed and architecture, memory performance and density and faster data transfers. Approaches for implementing 32- and 64-bit processes with silicon-on-insulator technology; Chip developed by Hewlett-Packard Co. which can cram 1.5 megabytes of cache.

Focuses on technological developments related to smart cards. Increasing popularity of multiple-function smart cards; Increased intelligence as a result of using faster and more powerful next-generation microcontrollers and central processing unit cores; Security concerns; Need for more storage in controllers to hold data and electronic funds information.

Describes how to create an optimized solution for embedded microprocessor applications using a logic-efficient central processing unit and instruction-set architecture called Xtensa developed by Tensilica Inc. Differentiation of applications by examining program size, instruction mix and frequency and degree of instruction and data access; Importance of having the right amount of instruction cache.

Examines the challenge of designing a highly integrated system-on-a-chip solution. Demand for higher levels of functionality and performance; Reductions in feature sizes; Integration of programmable logic or a block of gate-array gates on the chip; Combination of complementary metal oxide semiconductors (CMOS) and silicon-germanium; High-visibility debug interface development.

Highlights the research papers at the 1998 International Electron Devices Meeting (IEDM) about computer random access memory (RAM). Samsung Electronics Corp.'s paper about improving storage cell-structure for use in 16-gigabit dynamic RAMs; Samsung's paper examining an enhanced dynamic RAM memory structure; Toshiba Corp.'s paper examining trends in memory cell approaches.

Focuses on the competition between microprocessor manufacturers in the United States in improving the clock speed of x86 processors in order to deliver supercomputing performance on the desktop. Demand for processors that are capable of four-way or N-way multiprocessing; Aggressive use of multilevel metallization and deep-submicron lithography; Domination of Intel's x86 processor in the market.

Focuses on the evolution of laser drivers of optical communication systems and optical data links. Availability of complete optical transmitters with the laser driver and laser diode in one package; Need for data interfaces to be crafted from individual building blocks.

Cites the emergence of new electronic circuit techniques and processes in reducing operating voltage and power drain. Sun Microelectronics Inc.'s UltraSPARC III; Leveraging of sub-threshold effects to create high-performance circuits; Schemes that use dual threshold voltage levels; Reduction of the I/O signal levels; Focus on standard, deep-submicron CMOS technology. INSET: Leveraging sub-threshold logic..

Reports that advances in the complex, programmable logic devices (CPLD) have challenged field programmable gate arrays. List of CPLD manufacturers; Technique for lowering manufacturing cost of electrically erasable technology without compromising CPLD performance; Features of the Vantis MACH 5 series.

Features Lattice Semiconductor Corp.'s in-system programmable ispLSI 8000 line of complex programmable logic devices (CPLD). Key specifications; Basic architecture; Chip components of the CPLD line; Programmable output features.

Discusses how superscalar central processing units tackle throughput-intensive embedded needs with effective throughputs of 200 million instructions per second (MIPS). Reduced instruction set computers (RISC) and complex instruction set computers (CISC) processors; Incorporation of Level-1 and Level-2 caches on MIPS-family processor; Control and processing of multimedia data.