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Bilayer selectorless resistive random-access memories (RRAM) have been demonstrated by utilizing the intrinsic nonlinear resistive switching (RS) characteristics, without additional transistor or a selector integration. The bilayer structures, i.e. high-k layer/low-k layer stacks, are highly scalable while suppressing the sneak path currents (SPC) and reading error in the crossbar RRAM array. The nonlinearity (NL) modulation is also investigated by different operating schemes, and a multilevel cell application is demonstrated with the current-sweep method. The results provide additional insights into the development and optimization of bilayer selectorless RRAMs with high nonlinearity, good memory window, and low switching energy (∼ 40 pJ/bit), which enable the high-density storage and low-power crossbar array memory applications.

The ever‐increasing processing power demands of digital computers cannot continue to be fulfilled indefinitely unless there is a paradigm shift in computing. Neuromorphic computing, which takes inspiration from the highly parallel, low‐power, high‐speed, and noise‐tolerant computing capabilities of the brain, may provide such a shift. Many researchers from across academia and industry have been studying materials, devices, circuits, and systems, to implement some of the functions of networks of neurons and synapses to develop neuromorphic computing platforms. These platforms are being designed using various hardware technologies, including the well‐established complementary metal‐oxide semiconductor (CMOS), and emerging memristive technologies such as SiOx‐based memristors. Herein, recent progress in CMOS, SiOx‐based memristive, and mixed CMOS‐memristive hardware for neuromorphic systems is highlighted. New and published results from various devices are provided that are developed to replicate selected functions of neurons, synapses, and simple spiking networks. It is shown that the CMOS and memristive devices are assembled in different neuromorphic learning platforms to perform simple cognitive tasks such as classification of spike rate‐based patterns or handwritten digits. Herein, it is envisioned that what is demonstrated is useful to the unconventional computing research community by providing insights into advances in neuromorphic hardware technologies.

We explore overcoming the non-oxidizing environment requirement issues in silicon oxide (SiOx) based memristors and investigate potential next steps for use of SiOx as a memristor material. A SiOx/HfOx stacked material was engineered, developed and tested to verify operation of the SiOx-based memristors, and the stacked material exhibits interfacial proton accumulation leading to ultra-low-voltage operation (

Selectorless graphite-based resistive random-access memory (RRAM) has been demonstrated by utilizing the intrinsic nonlinear resistive switching (RS) characteristics, without an additional selector or transistor for low-power RRAM array application. The low effective dielectric constant value (k) layer of graphite or graphite oxide is utilized, which is beneficial in suppressing sneak-path currents in the crossbar RRAM array. The tail-bits with low nonlinearity can be manipulated by the positive voltage pulse, which in turn can alleviate variability and reliability issues. Our results provide additional insights for built-in nonlinearity in 1R-only selectorless RRAMs, which are applicable to the low-power memory array, ultrahigh density storage, and in-memory neuromorphic computational configurations.

Resistive random access memory (RRAM) using various metal oxides (i.e., SiO2[1], HfO2, NiO[2], Al2O3, NbO) have attracted much attentions since the current nonvolatile memory (NVM) has been approaching the scaling limit. Meanwhile, selector devices are essential to address the sneak path issue which causes reading errors and hinders the implementation of RRAM in high-density cross-bar array architecture [3-4]. However, additional selector devices, e.g. a commonly proposed one selector-one resistor (1S-1R) design, increases the process complexity and cost. In this work, selectorless 1R RRAM devices have been demonstrated by utilizing the nonlinear (NL) resistive switching (RS) characteristics. Pulse operation voltage variation tolerance on SiOx-based stacking structures has also been characterized. The starting substrates are heavily-doped N+ Si wafers, and titanium nitride of 200 nm thickness was deposited on N+ Si substrate as bottom electrode. Then, 9 nm of SiOx and 4 nm of HfOx were deposited as RS dielectric layers for bilayer (HfOx/SiOx) structures by RF sputtering method. Pt (165nm) was deposited as top electrodes for RRAM devices (Fig. 1). Fig. 2 shows bipolar RS I-V characteristics during DC voltage sweeps for single-layer HfOx and bilayer devices. Both SET and RESET voltages are lower in single-layer HfOx devices than in bilayer devices possibly due to higher oxygen concentration. The SET voltage of single-layer HfOx devices is about 0.2 V lower than of single-layer SiOx devices, and RESET voltage is reduced to half (~ 0.5 V) with inserting a HfOx stack layer, which is potentially beneficial for low voltage operating applications. Also, the RESET current is critical for overall switching power in RRAM applications, is ~1 mA and has been found to be independent of the thickness ratio of stacks. Comparing the bilayer structure to the single-layer HfOxstructure, the current at -0.2 V is reduced from ~10-4 to ~10-6 A. It depicts that there was significantly increased resistance at low voltage region, which is proposed as a solution for sneak path issue in crossbar array applications. Nonlinearity (NL) is defined as the ratio of the current at full read voltage (i.e. -0.6 V) to the current at 1/3 read voltage (-0.2 V). The higher nonlinearity, the better ability is to avoid the sneak current interference. The NL characteristics in ILRS of all the devices are showed in Fig. 3. With a thin SiOx layer (2 nm) on the bottom of HfOx (11 nm) layer, the NL is ~3x in comparison to the single-layer HfOx layer devices. Based on our results, the bilayer RRAM device has been found to show the highest NL among the SiOx-based stacking structures. This makes SiOx-based bilayer devices a potential candidate for 1R selectorless RRAMs. To evaluate the voltage variation tolerance in pulse operation, the reset stop voltage effect has been studied. The RS I-V was characterized with increasing RESET stop voltage from -1.4 to -2.6 V for the bilayer and trilayer devices (Fig. 4). For bilayer devices, the high resistance state (HRS) resistance and memory window increase with increasing RESET stop voltage (Fig. 5). The bilayer devices with higher SET/RESET voltage variation tolerance (less variation below stop voltage of 2.2 V) and have been found to exhibit better NL characteristics (~10) than the trilayer devices, which shows larger switching voltage variation with changing reset stop voltage (Fig.6). In this study, build-in nonlinear characteristics have been realized for the SiOx-based one-resistor (1R) device without an additional diode or a selector. The highly nonlinear characteristics observed in SiOx-based bilayer devices are desirable in avoiding the read error and preventing sneak-path currents in crossbar arrays. Our results show that SiOx-based bilayer devices are promising for high-density, low-power, selectorless RRAM applications. Figure 1

In this paper, implication (IMP) operations are demonstrated in a circuit with two SiOx-based memristors and a CMOS transistor. Specifically, a circuit with two one-diode and one-resistor (1D1R) memory elements and a transistor are designed to perform the IMP operations. A circuit consisting of a $4 \times 4$ crossbar 1D1R memristor array together with selection transistors is proposed and used to realize the functionality of a one-bit, full adder in 43 steps. Compared with CMOS logic circuits, the advantages and disadvantages of memristor-enabled logic circuits are discussed. This result suggests that the memristor-enabled logic circuit is most suitable for low-power and high-density applications, as well as a simple and robust approach to realize programmable memcomputing chips compatible with large-scale CMOS manufacturing technology.

Resistive random access memory (RRAM) is a leading candidate in the race towards emerging nonvolatile memory technologies. The sneak path current (SPC) problem is one of the main difficulties in crossbar memory configurations. RRAM devices with desirable properties such as a selectorless, 1R-only architecture with self-rectifying behavior are potential SPC solutions. In this work, the intrinsic nonlinear (NL) characteristics and relaxation characteristics of bilayer high-k/low-k stacked RRAMs are presented. The intrinsic nonlinearity reliability of bilayer selectorless 1R-only RRAM without additional switches has been studied for their ability to effectively suppress SPC in RRAM arrays. The relaxation properties with resistive switching identification method by utilizing the activation energy (Ea) extraction methodology is demonstrated, which provides insights and design guidance for non-uniform bilayer selectorless 1R-only RRAM array applications.

Characteristics of HfOx-based resistive switching memory (RRAM) in Al/HfOx/Al and Al/AlOx/HfOx/Al structures were studied using a dynamic conductance method. Step-like RESET behaviors as well as pre- and post-RESET regions of operation were characterized. The results indicated that defects at the oxide interface caused cycling issues in the Al/AlOx/HfOx/Al structure. No such RESET behavior was observed for the Al/HfOx/Al structure. Current induced over-heating, which caused an early RESET event, could be avoided using current-sweep technique that caused less electrical and thermal stress in localized regions. The experimental results not only provided insights into potential reliability issues and power management in HfOx-based RRAM, but also helped clarifying the resistive switching mechanisms.

Oxide based resistive switching memory are the promising candidates for future non-volatile memory according to fast programing, low power operation, scalability and compatibility to the current CMOS process. Among, SiOx single layer resistive switching devices have been widely studied and characterized. The SiOx single layer resistive memory has good compatibility to CMOS fabrication process. However, it can only be programmed under the vacuum or non-oxidized ambient. Also, the previous results reported on SiOx-based memristors indicate that the electroforming and programming voltage is relatively higher than the other dielectric materials and obstructed for low-power applications. In this work, by using SiOx/HfOx stacking engineering, we have developed a low-voltage operation (< 2V) for SiOx-based ReRAM. The results show that with HfOx (3nm) on bottom, the metal-insulator-semiconductor (MIS) structures exhibit resistive switching at low voltage (x-based MIS devices which exhibit bipolar-type resistive switching behaviors with small memory window.Clearly, SiOx/HfOx stacking optimization not only maintains the RS behaviors even in air environment without any programming window degradation, but also further reduces the switching voltage below 2V. Figure 1 shows the results of three different structures, including SiOx single layer memristor, SiOx/HfOx bilayer memristor and HfOx single layer memristor. In terms of operation environment condition, inserting the HfOx layer would help the SiOx memristor to be able to programmed either under a pressure of 1E-4 torr or in the atmosphere. The HfOx single layer memristor has the lowest electroforming voltage of 2.3 V, and which in SiOx/HfOx stacks has been reduced significantly to 5 V comparing which of 14 V for SiOx single layer. For the SiOx/HfOx bilayer, a memory window of 4 decades is achieved and comparable to that of SiOx single layer, and larger than that of single layer HfOx by 2 decades. In terms of operation voltage, the set voltage is reduced from 4V to 2 V and the reset voltage is also suppressed significantly from 10 V to 0.3 V by inserting the 3 nm HfOx layer. Figure 2 shows the TEM images of both SiOx single layer memristor and SiOx/HfOx bilayer memristor. The 3 nm HfOx was deposited on N+ Si wafer at 250 oC by atomic layer deposition followed by 30 nm SiO2 deposition using e-beam evaporator and 160 nm TaN depositing by sputtering. Figure 3. The single layer HfOx-based MIS devices resistive switching behaviors. (a) The electroforming process, resistive switching behaviors in 20 times cycling. (b) The switching voltage (SET/RESET) and states (HRS/LRS) distribution. Figure 1

In this work, we investigated SiO(x)-based interfacial resistive switching in planar metal-insulator-metal structures using physical/chemical/electrical analyses. This work helps clarify the interfacial reaction process and mechanism in SiO(x), and also shows the potential for high temperature operation in future nonvolatile memory applications.

We propose a research topic to comprehensively understand the intrinsic unipolar SiOx-based resistive-switching random-access memory (ReRAM) characteristics and mechanisms that can provide deep insights of device design and performance improvement for next-generation nonvolatile memory applications, as required for low-power portable electronics, highly-integrated of compact memory design, and other applications. Several main research targets will be pursued. Firstly, we will investigate device structures, material compositions and electrical characteristics to realize ReRAM cells with high ON/OFF ratio, low static power consumption, low switching power, and high readout-margin using CMOS compatible SiOx-based materials in both metal-insulator-semiconductor (MIS) and metal-insulator-metal (MIM), and one diode - one resistive switching element (1D-1R) architectures. These ideas will be combined with the use of horizontal and vertical device structure designs (active device size and thickness), composition optimization (SiOx, x < 2), electrical controlling (compliance current limitation, stopped voltage sweeping, and polarity effect) and external factors (series-resistance and ambient effects) for understanding and characterizations of resistive switching mechanism. Secondly, modeling of resistive switching mechanism, including temperature effect, pulse response and carrier transport behaviors will be performed, to develop a compact model in energy diagram, trap-level information, dipole polarization in SiOx resistive switching layer, even for computer-aided design (CAD) in very-large-scale integration (VLSI) design. Finally, for the first time, an intriguing non-Von Neumann computing architecture, named synapse-based neuromorphic system, will be demonstrated in SiOx-based ReRAM, combining with bio-inspiration and biomimetics process illustrations. The novel applications in the physiology and pathology discussions in reactive oxygen species (ROS) production and regulation processes will be clarified. This work will present the comprehensively investigation of SiOx-based resistive switching characteristics, mechanisms, applications for future post-CMOS devices era.

Electroforming and resistive switching in SiO2 materials are investigated by controlling the annealing temperature, etching time and operating ambient. Thermal anneal in reducing ambient lowers electroforming voltage to 10 nm from the electrode edge in devices with continuous SiO2 layers. Switching unpassivated devices fails in 1 atm air and pure O2/N2, with the recovery of vacuum switching at ∼4.6 V after switching attempts in O2/N2 and at ∼9.5 V after switching attempts in air. Incorporating a hermetic passivation layer enables switching in 1 atm air. Discussions of defect energetics and electrochemical reactions lead to a localized switching model describing device switching dynamics. Low-frequency noise data are consistent with charge transport through electron-trapping defects. Low-resistance-state current for

For the first time, a comprehensive study of Vanadium oxide-based selector characteristics with a universal model observed by thermal and electrical induced threshold switching (TS) phenomena at interface is presented in this work. The model can explain that the resistance evolution by thermal temperature in TS behaviors, as well as the resistance gradually increases with cycling (“seasoning effect”). Compatible current density (107∼109 A/cm2) and selectivity (∼100) with physical understanding of evolution in energy barrier and MIT metallic state modulation are studied. The results show a promising design guideline for future storage-class memory (SCM) applications.

We report on a highly compact, one diode-one resistor (1D-1R) nanopillar device architecture for SiOx-based ReRAM fabricated using nanosphere lithography (NSL). The intrinsic SiOx-based resistive switching element and Si diode are self-aligned on an epitaxial silicon wafer using NSL and a deep-Si-etch process without conventional photolithography. AC-pulse response in 50 ns regime, multibit operation, and good reliability are demonstrated. The NSL process provides a fast and economical approach to large-scale patterning of high-density 1D-1R ReRAM with good potential for use in future applications.

Recently, resistive random access memory (RRAM) using various metal oxides (i.e., SiO 2 [1], HfO 2 , NiO[2], Al 2 O 3 , NbO) have attracted a lot of attentions since the current nonvolatile memory (NVM) approaching the scaling limits. Meanwhile, the selector devices are essential to address the sneak path issue which causing the reading errors in high-packing-density cross-bar RRAM array. Several types of selector devices with threshold switching (TS) behavior has been investigated, such as rectifying diode[3], varistors[4], ovonic TS (OTS)[5], metal-insulator transition (MIT)[6] etc. In this work, the characteristics of electrically driven MIT (E-MIT) in both Nb-doped SrTiO 3 and HfO 2 -based selector devices has been investigated.

Intrinsic unipolar SiOx-based resistance random access memories (ReRAM) characterization, switching mechanisms, and applications have been investigated. Device structures, material compositions, and electrical characteristics are identified that enable ReRAM cells with high ON/OFF ratio, low static power consumption, low switching power, and high readout-margin using complementary metal-oxide semiconductor transistor (CMOS)–compatible SiOx-based materials. These ideas are combined with the use of horizontal and vertical device structure designs, composition optimization, electrical control, and external factors to help understand resistive switching (RS) mechanisms. Measured temperature effects, pulse response, and carrier transport behaviors lead to compact models of RS mechanisms and energy band diagrams in order to aid the development of computer-aided design for ultralarge-v scale integration. This chapter presents a comprehensive investigation of SiOx-based RS characteristics and mechanisms for the post-CMOS device era.

We realize a device with biological synaptic behaviors by integrating silicon oxide (SiOx) resistive switching memory with Si diodes to further minimize total synaptic power consumption due to sneak-path currents and demonstrate the capability for spike-induced synaptic behaviors, representing critical milestones for the use of SiO2-based materials in future neuromorphic computing applications. Biological synaptic behaviors such as long-term potentiation, long-term depression, and spike-timing dependent plasticity are demonstrated systemically with comprehensive investigation of spike waveform analyses and represent a potential application for SiOx-based resistive switching materials. The resistive switching SET transition is modeled as hydrogen (proton) release from the (SiH)2 defect to generate the hydrogenbridge defect, and the RESET transition is modeled as an electrochemical reaction (proton capture) that re-forms (SiH)2. The experimental results suggest a simple, robust approach to realize programmable neuromorphic chips compatible with largescale complementary metal-oxide semiconductor manufacturing technology.

Intrinsic unipolar SiOx-based Resistive-RAM (ReRAM) characteristics have been investigated. The cross-bar MIM structures have been examined under AC frequency response, by varying device area, temperature and current states. The results provide additional insights into the hopping/switching mechanisms. For the first time, by using SiOx/HfOx stacking engineering, we have developed a low-voltage operation (< 2V) for SiOx-based ReRAM. The SiOx/HfOx stacking optimization not only maintains the RS behaviors even in air environment without any programming window degradation, but also further reduces the switching voltage below 2V.

In this paper, we fabricated and investigated the electroforming process and switching behavior of Al/SiOx/Si MOS resistive random access memory (RRAM) devices. The switching mechanism and device performance including forming voltage, set/reset voltage, on/off ratio and retention have been analyzed. Memory structure was formed, or electroformed by applying voltage across the MOS device. This SiOx RRAMs show a unique switching behavior with set voltage lower than reset voltage. Thus, unlike other RRAMs, our RRAM devices do not need current compliance in the switching process. Furthermore, our device utilizes SiOx, which has been extensively used and is completely compatible with CMOS technology. The results show that introducing a plasma treatment process and optimizing the plasma conditions significantly reduced electroforming voltage.

ThefilamentarygrowthandswitchingmechanismofSiOx-basedresistiveswitchingrandomaccessmemorieshavebeeninvestigated. In test structures with two devices connected in series, it has been found that the applied voltage in the first electroforming sweep equally stressed the SiOx in both devices. Therefore, it is concluded that a conducting filament (CF) grows in both devices. The resistance switching is induced by the rupture and recovery in a weak spot of the CF. The weak spot formation is a random process in the CF and could be anywhere along the CF. Once the weak spot is established, the rupture and recovery is localized in that particular region and independent of applied voltage polarity.

We realize a device with biological synaptic behaviors by integrating silicon oxide (SiOx) resistive switching memory with Si diodes. Minimal synaptic power consumption due to sneak-path current is achieved and the capability for spike-induced synaptic behaviors is demonstrated, representing critical milestones for the use of SiO2–based materials in future neuromorphic computing applications. Biological synaptic behaviors such as long-term potentiation (LTP), long-term depression (LTD) and spike-timing dependent plasticity (STDP) are demonstrated systematically using a comprehensive analysis of spike-induced waveforms and represent interesting potential applications for SiOx-based resistive switching materials. The resistive switching SET transition is modeled as hydrogen (proton) release from (SiH)2 to generate the hydrogen bridge defect and the RESET transition is modeled as an electrochemical reaction (proton capture) that re-forms (SiH)2. The experimental results suggest a simple, robust approach to realize programmable neuromorphic chips compatible with large-scale CMOS manufacturing technology.

Resonant cavity detectors based on III–V materials have been designed, grown entirely by molecular beam epitaxy, fabricated, and tested. They offer a low noise (dark current densities of 0.4 mA/cm2 were measured at 298 K, close to the predicted value of 0.31 mA/cm2), narrow response detector (full width at half maximum of 57 nm in GaSb and 45 nm in InAs) in the mid-infrared region, with future applications in spectroscopy, gas sensing, and optical communications.

In this work, one diode-one resistor (1D-1R) SiO x -based resistive switching (RS) elements were fabricated using PN Si diode as a selector to eliminate sneak-path issues. Our work and results include: 1) demonstrating sub-μs pulsed programming; 2) rectification ratio > 106 (meeting ITRS roadmap criteria) for integrated 1D-1R cross-bar arrays; 3) multi-bit operation; 4) 106 endurance cycles; and 5) robust read/write disturbance immunity for unselected cells in 16×16 1D-1R arrays.

Intrinsic unipolar SiO x -based Resistive-RAM (ReRAM) characteristics and resistive switching mechanisms have been investigated in TiW/SiO x /TiW structure. The cross-bar (metal-insulator-metal) MIM structures have been examined and optimized, and SiO x composition has been varied. Current transport behaviors of multilevel states, switching layer polarization, proposed defect transformations and energy band diagrams of SET and RESET processes have been modeled to provide insights for optimization to obtain high yield and auto-forming capability.

Sneak path current is a severe hindrance for the application of high-density resistive random-access memory (RRAM) array designs. In this work, we demonstrate nonlinear (NL) resistive switching characteristics of a HfO x /SiO x -based stacking structure as a realization for selector-less RRAM devices. The NL characteristic was obtained and designed by optimizing the internal filament location with a low effective dielectric constant in the HfO x /SiO x structure. The stacking HfO x /SiO x -based RRAM device as the one-resistor-only memory cell is applicable without needing an additional selector device to solve the sneak path issue with a switching voltage of ~1 V, which is desirable for low-power operating in built-in nonlinearity crossbar array configurations.

The effects of incorporating a thin silicon layer into a SiO2-based resistive-switching random access memory are presented. An improved performance, including a lower electroforming voltage and a more stable device current in the high-resistance programmed state, has been achieved by physical vapor deposition of a thin silicon layer onto the sidewall region of the device. Tristate pulse endurance performance over 106 cycles has been demonstrated. The programmed data show immunity to read disturb testing at 1 V and can be sustained up to 150°C thermal exposure. It is concluded that the improved performance is due to formation of a more robust and more uniform conducting filament. As a result of this advantage, stable tristate programming can be realized in the SiO2-based resistive memory device.

A voltage-induced unidirectional threshold resistive switching has been reported for Au/NiO/Nb:SrTiO3 devices fabricated by pulsed laser deposition. The devices show the threshold resistive switching behavior only for the positive voltages, determined by the forming process. The current-voltage (I-V) and capacitance-voltage (C-V) characteristics of the as-grown samples with different thicknesses suggest that the I-V and C-V properties are dominated by the Schottky junction at the NiO/Nb:SrTiO3 interface and NiO film, respectively, indicating the formation of conductive filaments in NiO film. Furthermore, the effect of NiO-film thickness on the resistive switching, as well as the I-V and C-V characteristics, indicates that the unidirectional threshold resistive switching originates from the combined contributions of the interfacial Schottky junction modulation and the bipolar threshold switching related to the unstable conductive filament in NiO film. Our research results provide additional insights into t...

Resistive random access memories (ReRAM) has attracted tremendous attention as a promising candidate for non-volatile memory. ReRAM can be classified into two categories: unipolar and bipolar memory. The advantage of unipolar memory is that it can be integrated into simple 1D-1R architecture with low static power consumption and constrained sneak-path issue. This is because unipolar memory does not require opposite voltage polarities for on/off switching [1]. SiO x has long been used as gate dielectrics for MOSFET and recently proved to be an active unipolar ReRAM material [2, 3]. Here we report SiO x -based 1D-1R high density nanopillar ReRAM via nanosphere lithography.

In conclusion, the voltage-triggered SET mechanism and self-compliance characteristics have been studied in SiOx-based RRAM. A controllable program window is demonstrated, and further understanding is obtained using a dynamic conductivity method to provide insights into filament and GAP characteristics. These parameters not only help identify RS mechanisms, but also aid construction of a model to predict device operating performance for future device designs and applications.

A highly compact, one diode - one resistor (1D-1R) nano-pillar device architecture has been demonstrated using nano-sphere lithography (NSL) to fabricate SiO x -based resistive switching (RS) memory. The intrinsic SiO x -based resistive switching element and Si-based PN diode are self-aligned on the epitaxial silicon wafer using NSL and a deep-Si-etch process without using conventional photolithography. The DC electrical performance, an AC pulse response in the 50 ns regime, capability for multi-bit operation, and high readout margin immunity for sneak path issue demonstrate good potential for high-speed nonvolatile memory (NVM). The NSL fabrication process is an efficient, economical approach to enable large-scale patterning of 1D-1R architectures while providing excellent NVM performance for future applications.

The charge-trapping characteristics and trap levels of SiOx-based (TaN/SiO2/n++ Si-substrate) resistive switching memory (RS) have been investigated. Multilevel operation under compliance current control is demonstrated and current transport behavior is analyzed using the normalized conductance of low resistive state (LRS) and high resistive state (HRS). Temperature dependence of I-V characteristics indicates that corresponding trap-level depths and hopping distance are consistent with Frenkel-Poole emission and hopping conductance with voltage-dependent activation energy. In the high-voltage region in LRS, Fowler-Nordheim fitting indicates a weak dependence of tunneling distance on temperature, whereas the effective filament area shows a strong dependence with a calculated filament radius of about 10nm. SEM images of small gaps formed in a planar structure and EDX analysis indicate oxygen-deficient regions within the gap. Our experimental results not only provide additional insights into the trap-level system of SiOx-based RS memory but also help to construct a physical picture for the switching mechanism.

The electrical characteristics of SiO x -based complementary resistive switching (CRS) memristor have been investigated. Post-deposition annealing (PDA: 500°C 5min in O 2 ) of TaN/SiO 2 /n++ Si-substrate CRS memristor has been found to reduce operational variation in device characteristics, as well as improve the electrical stability during repeated switching. In this work, we have also studied the effects of sweeping polarity, operating temperature, electrode material and dimension scaling. Our experimental results not only provide additional insights into optimization of the SiO x -based CRS memory but also help in constructing a physical picture for the switching mechanism.

Vertically aligned carbon nanotube (CNT) arrays can provide the required combination of high thermal conductivity and mechanical compliance for thermal interface applications. Much work in the last 15 years has focused on improving the quality and intrinsic thermal conductivity of the nanotube arrays. Currently the thermal interface resistance between nanotube arrays and surrounding materials limits the overall thermal performance. To reduce this interface resistance, we propose coating the nanotube film with a continuous layer of metal. In this work, we electroplate 1 to 20 µm-thick continuous copper films directly on the carbon nanotube array. We measure the thermal conductivity of CNT arrays after electroplating using cross-sectional infrared microscopy. For low volume fraction, vertically-aligned carbon nanotubes arrays with copper electroplating (0.5 vol. %), the film thermal conductivity is nearly 3 W/m/K. These results demonstrate the feasibility of the electroplating method to coat CNT films.

ArF excimer laser‐enhanced photochemical vapor deposition of Si from Si2H6 in an UHV deposition chamber has been used to achieve Si epitaxy at temperatures as low as 250 °C. The system design criteria are discussed. Modified Schimmel etching/Nomarski microscopy, transmission electron microscopy, and reflection high energy electron diffraction have been used to study the microstructure of Si films as a function of laser power, substrate temperature and disilane partial pressure. The growth rates were observed to be linearly dependent on laser intensity and Si2H6 partial pressure. The morphology of the films is excellent and defects such as dislocation loops and stacking faults are not seen.

We describe the fabrication and operational characteristics of large area matrix addressable edge emitter arrays using nanolayered carbon films on 5"×5' glass substrates.

An ArF excimer laser has been used with the beam parallel to the Si(100) substrate in order to deposit homoepitaxial silicon films at temperatures from 250 to 350 °C with growth rates from 1 to 10 A min −1 . The growth involves photolytic decomposition of Si 2 H 6 and the generation and adsorption of growth precursors on the hydrogenated silicon surface. The deposition yield of solid silicon from photo-excited Si 2 H 6 is estimated to be 0.20 ± 0.04. Growth rates vary linearly with laser intensity and Si 2 H 6 partial pressure over the ranges 1–15 mJ cm − pulse −1 and 5–40 m Torr respectively. Epitaxy is maintained for temperatures above the threshold for thermal dissociation of surface (SiH 2 ) n chains at about 250 °C, and for temperatures below the onset of Si 2 H 6 pyrolysis and rapid thermal desorption of surface H 2 at about 350 °C. Epitaxy is achieved for laser intensities and Si 2 H 6 partial pressures that result in low initial photofragment concentrations (below 10 13 cm −3 ), and for total pressure and flow conditions such that there is little secondary photolysis of the initial photofragments. Very low defect density films in terms of stacking faults and dislocation loops (less than 10 5 cm −2 ), and excellent crystallinity, have been grown, as confirmed by Schimmel defect etching in conjunction with Nomarski microscopy, transmission electron microscopy, electron diffraction and in situ reflection high energy electron diffraction.

Homoepitaxial Si films were deposited using an ArF excimer laser beam parallel to the substrate to photodissociate Si2H6 at low temperatures (250–350 °C) under laser intensity and Si2H6 partial pressure conditions that result in low initial photofragment concentrations (< 1013 cm−3). Total pressure and flow conditions were chosen such that there is little secondary photolysis of the initial photofragments. The deposition yield of solid Si from photoexcited Si2H6 is estimated to be 0.20±0.04, indicating that in order for film growth to result solely from the primary products in ArF laser (193 nm) photolysis of Si2H6, a sticking coefficient ≥0.6 must be assigned to the dominant growth precursor. Growth rates vary linearly with laser intensity and Si2H6 partial pressure over a range of 1–15 mJ/cm2 pulse and 5–40 mTorr, respectively. Increasing the distance between the laser‐beam axis and the silicon substrate results in a reduction of the growth rate that can be explained by gas‐phase chemical reaction of th...

Low temperature silicon epitaxy has been achieved at substrate temperatures ranging from 250-350 o C using the 193 nm output of an ArF excimer laser to generate reactive growth precursors by photolytic decomposition of Si 2 H 6 . Growth rate dependencies on substrate temperature, Si 2 H 6 partial pressure, and laser photon flux density are presented. Growth rates are observed to vary linearly with laser beam power and Si 2 H 6 partial pressure, indicating that the overall growth rate is limited by the precursor generation rate

Defect characterization of epitaxial silicon films grown on lightly boron-doped Si (100) substrates by low temperature photo-enhanced chemical vapor Deposition (PCVD) using 193 nm ArF excimer laser dissociation of Si 2 H 6 in an ultra-high-vacuum (3×10 -9 Torr) chamber is discussed. The crystallinity was studied by in situ of reflection high energy electron diffraction (RHEED), and selected area electron diffraction in a transmission electron microscope (TEM), and defects such as stacking faults and dislocation loops were investigated by TEM and dilute Schimmel etching/Nomarski microscopy

Silicon homoepitaxial films have been grown by photodissociation of Si2H6 by the 193 nm line of an ArF excimer laser in an ultra-high vacuum system. Silicon epitaxy has been achieved in two ways: one, in which the laser shines into the chamber parallel to the substrate and another, in which the laser is directly incident on the substrate at grazing angles (87° with respect to the substrate normal). Controllable growth rates of 0.5–4A/min have been achieved for crystalline films by the first method using substrate temperatures as low as 250° C, Si2H6 partial pressures of 20 mTorr and photon flux densities of 1016 photons/pulse.cm2. In the second method, where the laser beam is directly incident on the wafer at grazing angles, very high growth rates of up to 80A/min have been achieved at 300° C, 20 mTorr Si2H6 partial pressure and a photon flux density of 2 × 1015 photons/pulse.cm2. A comparison of the microstructure of the films grown by the two methods is presented on the basis ofin situ reflection high energy electron diffraction (RHEED) analysis and selected area transmission electron microscopy (TEM) studies. In both cases, the growth rates are found to be linearly dependent on the photon flux density for the process parameter ranges studied.

Defect characterization of epitaxial silicon films grown on Si(100) lightly boron-doped wafers by low temperature photochemical vapor deposition using ArF excimer laser decomposition of Si 2 H 6 is discussed. The film morphology and crystallinity were investigated by defect etching-Nomarski optical microscopy, reflection high energy electron diffraction and transmission electron microscopy. The growth parameters such as laser power, Si 2 H 6 partial pressure and substrate temperature were varied to study the dependence of crystallinity on these parameters. Single-crystal films with a very low defect density were obtained at 0.08-0.7 W laser power, 5–20 mTorr Si 2 H 6 partial pressure and 250–350°C substrate temperature.

Self-compliance characteristics and reliability optimization are investigated in intrinsic unipolar silicon oxide (SiOx)-based resistive switching (RS) memory using TiW/SiOx/TiW device structures. The program window (difference between SET voltage and RESET voltage) is dependent on external series resistance, demonstrating that the SET process is due to a voltage-triggered mechanism. The program window has been optimized for program/erase disturbance immunity and reliability for circuit-level applications. The SET and RESET transitions have also been characterized using a dynamic conductivity method, which distinguishes the self-compliance behavior due to an internal series resistance effect (filament) in SiOx-based RS memory. By using a conceptual “filament/resistive gap (GAP)” model of the conductive filament and a proton exchange model with appropriate assumptions, the internal filament resistance and GAP resistance can be estimated for high- and low-resistance states (HRS and LRS), and are found to be independent of external series resistance. Our experimental results not only provide insights into potential reliability issues but also help to clarify the switching mechanisms and device operating characteristics of SiOx-based RS memory.

Using current-sweep measurements, the set process in SiOx-based resistive random access memory (RRAM) has been found to consist of multiple resistance-reduction steps. Variation in set behaviors was observed and attributed to different defect distributions in the resistance switching region. Physical mechanism of electroforming process is discussed, which further explains the observed variation of defect distributions. A compliance current study confirms that the achievable memory states of SiOx RRAM are determined by its set behavior. This finding provides additional insight on achieving multi-bit memory storage with SiOx RRAM.