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132 results on '"Butzen, Paulo"'

2. A Two-Level Approximate Logic Synthesis Combining Cube Insertion and Removal

Author

Ammes, Gabriel, Neto, Walter Lau, Butzen, Paulo, Gaillardon, Pierre-Emmanuel, and Ribas, Renato P.

Subjects
Computer Science - Other Computer Science, Computer Science - Hardware Architecture, Computer Science - Logic in Computer Science
Abstract

Approximate computing is an attractive paradigm for reducing the design complexity of error-resilient systems, therefore improving performance and saving power consumption. In this work, we propose a new two-level approximate logic synthesis method based on cube insertion and removal procedures. Experimental results have shown significant literal count and runtime reduction compared to the state-of-the-art approach. The method scalability is illustrated for a high error threshold over large benchmark circuits. The obtained solutions have presented a literal number reduction up to 38%, 56% and 93% with respect to an error rate of 1%, 3% and 5%, respectively., Comment: 5 Pages, submitted to IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Published
2021
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3. Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization

Author

Rai, Shubham, Neto, Walter Lau, Miyasaka, Yukio, Zhang, Xinpei, Yu, Mingfei, Fujita, Qingyang Yi Masahiro, Manske, Guilherme B., Pontes, Matheus F., Junior, Leomar S. da Rosa, de Aguiar, Marilton S., Butzen, Paulo F., Chien, Po-Chun, Huang, Yu-Shan, Wang, Hoa-Ren, Jiang, Jie-Hong R., Gu, Jiaqi, Zhao, Zheng, Jiang, Zixuan, Pan, David Z., de Abreu, Brunno A., Campos, Isac de Souza, Berndt, Augusto, Meinhardt, Cristina, Carvalho, Jonata T., Grellert, Mateus, Bampi, Sergio, Lohana, Aditya, Kumar, Akash, Zeng, Wei, Davoodi, Azadeh, Topaloglu, Rasit O., Zhou, Yuan, Dotzel, Jordan, Zhang, Yichi, Wang, Hanyu, Zhang, Zhiru, Tenace, Valerio, Gaillardon, Pierre-Emmanuel, Mishchenko, Alan, and Chatterjee, Satrajit

Subjects
Computer Science - Machine Learning
Abstract

Logic synthesis is a fundamental step in hardware design whose goal is to find structural representations of Boolean functions while minimizing delay and area. If the function is completely-specified, the implementation accurately represents the function. If the function is incompletely-specified, the implementation has to be true only on the care set. While most of the algorithms in logic synthesis rely on SAT and Boolean methods to exactly implement the care set, we investigate learning in logic synthesis, attempting to trade exactness for generalization. This work is directly related to machine learning where the care set is the training set and the implementation is expected to generalize on a validation set. We present learning incompletely-specified functions based on the results of a competition conducted at IWLS 2020. The goal of the competition was to implement 100 functions given by a set of care minterms for training, while testing the implementation using a set of validation minterms sampled from the same function. We make this benchmark suite available and offer a detailed comparative analysis of the different approaches to learning, Comment: In this 23 page manuscript, we explore the connection between machine learning and logic synthesis which was the main goal for International Workshop on logic synthesis. It includes approaches applied by ten teams spanning 6 countries across the world

Published
2020

7. An Improved Technique for Logic Gate Susceptibility Evaluation of Single Event Transient Faults

Author

Schvittz, Rafael B., Franco, Denis T., da Rosa, Leomar S., Jr., Butzen, Paulo F., Rannenberg, Kai, Editor-in-Chief, Soares Barbosa, Luís, Editorial Board Member, Goedicke, Michael, Editorial Board Member, Tatnall, Arthur, Editorial Board Member, Neuhold, Erich J., Editorial Board Member, Stiller, Burkhard, Editorial Board Member, Tröltzsch, Fredi, Editorial Board Member, Pries-Heje, Jan, Editorial Board Member, Kreps, David, Editorial Board Member, Reis, Ricardo, Editorial Board Member, Furnell, Steven, Editorial Board Member, Mercier-Laurent, Eunika, Editorial Board Member, Winckler, Marco, Editorial Board Member, Malaka, Rainer, Editorial Board Member, Metzler, Carolina, editor, Gaillardon, Pierre-Emmanuel, editor, De Micheli, Giovanni, editor, and Silva-Cardenas, Carlos, editor

Published
2020
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20. Routing Resistance Influence in Loading Effect on Leakage Analysis

Author

Butzen, Paulo F., Reis, André I., Ribas, Renato P., Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Monteiro, José, editor, and van Leuken, René, editor

Published
2010
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21. Subthreshold Leakage Modeling and Estimation of General CMOS Complex Gates

Author

Butzen, Paulo F., Reis, André I., Kim, Chris H., Ribas, Renato P., Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Azémard, Nadine, editor, and Svensson, Lars, editor

Published
2007
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29. Reliability Evaluation of Voters for Fault Tolerant Approximate Systems

Author

Balen, Tiago R., primary, Gonzalez, Carlos J., additional, Oliveira, Ingrid F. V., additional, Schvittz, Rafael B., additional, Added, Nemitala, additional, Macchione, Eduardo L. A., additional, Aguiar, Vitor A. P., additional, Guazzelli, Marcilei A., additional, Medina, Nilberto H., additional, and Butzen, Paulo F., additional

Published
2021
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33. Design considerations of a nonvolatile accumulator-based 8-bit processor

Author

Cagliari, Bruna Casagranda, Butzen, Paulo Francisco, and Brum, Raphael Martins

Subjects
Engenharia de sistemas, Nonvolatile processors, Magnetic tunnel junction, Memória (Informática), Nonvolatile flip-flops, Microeletrônica
Abstract

The rise of the Internet of Things (IoT) and theconstant growth of portable electronics have leveraged the con-cern with energy consumption. Nonvolatile memory (NVM)emerged as a solution to mitigate the problem due to its abilityto retain data on sleep mode without a power supply. Non-volatile processors (NVPs) may further improve energy savingby using nonvolatile flip-flops (NVFFs) to store system state,allowing the device to be turned off when idle and resume ex-ecution instantly after power-on. In view of the potential pre-sented by NVPs, this work describes the initial steps to imple-ment a nonvolatile version of Neander, a hypothetical processorcreated for educational purposes. First, we implemented Ne-ander in Register Transfer Level (RTL), separating the com-binational logic from the sequential elements. Then, the lat-ter was replaced by circuit-level descriptions of volatile flip-flops. We then validated this implementation by employinga mixed-signal simulation over a set of benchmarks. Resultshave shown the expected behavior for the whole instructionset. Then, we implemented circuit-level descriptions of mag-netic tunnel junction (MTJ) based nonvolatile flip-flops, usingan open-source MTJ model. These elements were exhaustivelyvalidated using electrical simulations. With these results, weintend to carry on the implementation and fully equip our pro-cessor with nonvolatile features such as instant wake-up.

Published
2021

34. A SPICE model for design of threshold current controlled memristive devices based applications

Author

Dias, Cesar de Souza and Butzen, Paulo Francisco

Subjects
Stateful logic, SPICE model, Simulação computacional, Threshold current, Material implication, Switching resistance, Memristor, Circuitos digitais, Microeletrônica
Abstract

This paper presents a generic SPICE model for threshold current controlled memristive devices. This work relates to mathematical development to allow this kind of behavior and it exhibits its relationship with the equivalent circuit adopted to achieve this goal. The operating logic is described and the code for its computational implementation is presented and explained. The functionality of the model implemented is demonstrated through several simulation experiments, whose results clearly show the switching resistance dependency on the electrical current through the device and highlight some important fingerprints of memristive devices. The acquisition and the data analysis from tests also help to prove the excellent convergence performance of the model presented and to elucidate the parameter settings. Finally, the paper reinforces the relevance of this new proposition by addressing one of its potential applications, demonstrating its use in the implementation of memristive stateful logic based on material implication.

Published
2021

35. Memristors : a journey from material engineering to beyond Von-Neumann computing

Author

Dias, Cesar de Souza and Butzen, Paulo Francisco

Subjects
Models, Applications, Devices, Memristors, Circuitos digitais, Microeletrônica
Abstract

Memristors are a promising building block to the next generation of computing systems. Since 2008, when the physical implementation of a memristor was first postulated, the scientific community has shown a growing interest in this emerging technology. Thus, many other memristive devices have been studied, exploring a large variety of materials and properties. Furthermore, in order to support the design of prac-tical applications, models in different abstract levels have been developed. In fact, a substantial effort has been devoted to the development of memristive based applications, which includes high-density nonvolatile memories, digital and analog circuits, as well as bio-inspired computing. In this context, this paper presents a survey, in hopes of summarizing the highlights of the literature in the last decade.

Published
2021

40. Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization

Author

Rai, Shubham, primary, Neto, Walter Lau, additional, Miyasaka, Yukio, additional, Zhang, Xinpei, additional, Yu, Mingfei, additional, Yi, Qingyang, additional, Fujita, Masahiro, additional, Manske, Guilherme B., additional, Pontes, Matheus F., additional, da Rosa, Leomar S., additional, de Aguiar, Marilton S., additional, Butzen, Paulo F., additional, Chien, Po-Chun, additional, Huang, Yu-Shan, additional, Wang, Hoa-Ren, additional, Jiang, Jie-Hong R., additional, Gu, Jiaqi, additional, Zhao, Zheng, additional, Jiang, Zixuan, additional, Pan, David Z., additional, de Abreu, Brunno A., additional, de Souza Campos, Isac, additional, Berndt, Augusto, additional, Meinhardt, Cristina, additional, Carvalho, Jonata T., additional, Grellert, Mateus, additional, Bampi, Sergio, additional, Lohana, Aditya, additional, Kumar, Akash, additional, Zeng, Wei, additional, Davoodi, Azadeh, additional, Topaloglu, Rasit O., additional, Zhou, Yuan, additional, Dotzel, Jordan, additional, Zhang, Yichi, additional, Wang, Hanyu, additional, Zhang, Zhiru, additional, Tenace, Valerio, additional, Gaillardon, Pierre-Emmanuel, additional, Mishchenko, Alan, additional, and Chatterjee, Satrajit, additional

Published
2021
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