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I.IntroductionWith overlay requirements getting more and more critical, a lot of work has been done in the industry to improve the overlay correction capability by using high order process corrections, corrections per exposure and heating control (lens and reticle). Another part of the overlay budget is linked to our ability to control and stabilize it through time as well as being reactive to changes via the advanced process control system of the fab (APC)[1]. This paper describes the steps taken from an individual feedback loops configuration (one technology, one or several similar layers) to large perimeter overlay run- to-run for a high-mix 300mm semiconductor logic fab[2]. First, a multivariate APC system is defined with all the specificities needed to enable a large perimeter configuration. Then, technology/layer grouping is explained as well as filters and limits settings to start the new feedback loops simulation. The simulation phase or "learning mode" allows to have an overview on the expected gains: enhanced reactivity to parameters drift and easier maintenance by engineers in charge of following overlay run-to-run, which indirectly leads to better overall APC performance. After overlay large perimeter activation, the alert number drastically decreases, risk of measurement sampling is minimized in the fab and a similar approach is started on energy large perimeter (CD: Critical Dimensions).

DSA patterning is a promising solution for advanced lithography as a complementary technique to standard and future lithographic technologies. In this work, we focused on DSA grapho-epitaxy process-flow dedicated for contact hole applications using polystyrene-b-poly(methyl methacrylate) (PS-b-PMMA) block copolymers. We investigated the impact on the DSA performances of the surface affinity of a guiding pattern design by ArF immersion lithography. The objective was to control and reduce the polymer residue at the bottom of the guiding pattern cavities since it can lead to lower a DSA-related defectivity after subsequent transfer of the DSA pattern. For this purpose, the DSA performances were evaluated as a function of the template surface affinity properties. The surface affinities were customized to enhance DSA performances for a PS-b-PMMA block copolymer (intrinsic period 35nm, cylindrical morphology) by monitoring three main key parameters: the hole open yield (HOY), the critical dimension uniformity (CDU-3σ) and the placement error (PE-3σ). Scanning transmission electron microscopy (STEM) was conjointly carried out on the optimized wafers to characterize the residual polymer thickness after PMMA removal. The best DSA process performances (i.e., hole open yield: 100%, CDU-3σ: 1.3nm and PE-3σ: 1.3nm) were achieved with a thickness polymer residue of 7 nm. In addition, the DSA-related defectivity investigation performed by review-SEM enabled us to achieve a dense (pitch 120nm) contact area superior to 0.01mm2 free of DSA-related defects. This result represents more than 6x105 SEM-inspected valid contacts, attesting the progress achieved over the last years and witnessing the maturity of the DSA in the case of contact holes shrink application.

Directed Self-Assembly (DSA) is a well-known candidate for next generation sub-15nm half-pitch lithography. [1-2] DSA processes on 300mm wafers have been demonstrated for several years, and have given a strong impression due to finer pattern results. [3-4] On t he other hand, specific issues with DSA processes have begun to be clear as a result of these recent challenges. [5-6] Pattern placement error, which means the pattern shift after DSA fabrication, is recognized as one of these typical issues. Coat-Develop Track systems contribute to the DSA pattern fabrication and also influence the DSA pattern performance. [4] In this study, the placement error was investigated using a simple contact-hole pattern and subsequent contact-hole shrink process implemented on the SOKUDO DUO track. Thus, we will show the placement error of contact-hole shrink using a DSA process and discuss the difference between DSA and other shrink methods.

In this paper, we focus on the directed-self-assembly (DSA) application for contact hole (CH) patterning using polystyrene-b-poly(methyl methacrylate) (PS-b-PMMA) block copolymers (BCPs). By employing the DSA planarization process, we highlight the DSA advantages for CH shrink, repair and multiplication which are extremely needed to push forward the limits of currently used lithography. Meanwhile, we overcome the issue of pattern densityrelated- defects that are encountered with the commonly-used graphoepitaxy process flow. Our study also aims to evaluate DSA performances as function of material properties and process conditions by monitoring main key manufacturing process parameters: CD uniformity (CDU), placement error (PE) and defectivity (Hole Open Yield = HOY). Concerning process, it is shown that the control of surface affinity and the optimization of self-assembly annealing conditions enable to significantly enhance CDU and PE. Regarding materials properties, we show that the best BCP composition for CH patterning should be set at 70/30 of PS/PMMA total weight ratio. Moreover, it is found that increasing the PS homopolymer content from 0.2% to 1% has no impact on DSA performances. Using a C35 BCP (cylinder-forming BCP of natural period L0 = 35nm), high DSA performances are achieved: CDU-3σ = 1.2nm, PE-3σ = 1.2nm and HOY = 100%. The stability of DSA process is also demonstrated through the process follow-up on both patterned and unpatterned surfaces over several weeks. Finally, simulation results, using a phase field model based on Ohta-Kawasaki energy functional are presented and discussed with regards to experiments.

Two seed deposition hardware are compared in this paper: a standard Self Ionized Plasma (SIP) standard chamber and a new generation chamber allowing Cu deposition and re-sputtering simultaneously. TEM characterizations exhibits better features coverage for new seed generation thank to process fine tuning. It induces defectivity improvement and void density is reduced with new hardware. Furthermore, reliability performances are improved without degrading parametrical results.

Bi-directional current stressing was used for monitoring electromigration (EM) lifetime evolution in 45nm node interconnects. Experimental results show that an initial bimodal distribution of lifetimes can be modified into a more robust mono-modal distribution. Since the bi-directional tests provide successive void nucleation and void healing phases, the Cu microstructure is thought to evolve once the formed void is filled thanks to EM induced matter displacement. FEM modeling is used to compare the predicted location of void nucleation for given microstructures at the cathode end: a multigrain structure is compared to a perfect bamboo microstructure. Experimental and modeling results let us assume that small grains (

A 32nm node BEOL integration scheme is presented with 100nm metal pitch at local and intermediate levels and 50nm via size through a M1-Via1-M2 via chain demonstrator. To meet the 32nm RC performance specifications, extreme low-k (ELK) porous SiOCH k=2.3 is introduced at line and via level using a Trench First Hard Mask dual damascene architecture. Parametrical results show functional via chains and good line resistance. Integration validation of ELK porous SiOCH k=2.3 is investigated using a multi-level metallization test vehicle in a 45nm mature generation.

International audience; SiOCH low-k dielectrics introduction in copper interconnects associated to the critical dimensions reduction in sub-45-nm node technologies is a challenge for reliability engineers. Circuit wear-out linked to low-k dielectric breakdown is now becoming a major concern. With line-to-line spacing reduction, the control of the line shape and of the spacing uniformity within a wafer is becoming first-order parameters governing the low-k dielectric reliability. Improving the low-k reliability requires to discriminate each topological effect and to quantify its impact on the lifetime at product level. This paper demonstrates that the copper line shape induces a preferential breakdown of the dielectric close to the SiOCH/SiCN capping even at nominal voltage. The impact of the line edge roughness is studied with the introduction of a simple analytical model. Moreover, the impact of the roughness on the product lifetime has been quantified. It is demonstrated. that the line-to-fine spacing variation is less critical at the operational voltage than at high voltage stress. Finally, the impact of the spacing uniformity within the wafer and from wafer to wafer (reflecting the spacing fluctuation from product to product) on the Weibull shape is quantified and reported to be voltage-dependent in agreement with the experimental detail.

Contact hole patterns are becoming one of the most challenging lithographic process for 45nm node and below. In this study, we first screen some 193nm resist formulations to achieve 80nm contact holes with a DOF superior to 250nm for dense pitches, 150nm for isolated with immersion lithography and focus scan option. In addition to this process window requirement, we also consider the MEEF behaviour of these resist samples as a function of the lithographic process. We encountered a trade-off between DOF performance and MEEF. With our best sample, large DOF is promoted by focus scan and photoacid diffusion whereas it strongly affects the MEEF value. Process tricks which tend to enhance chemical contrast within the resist, such as overbaking PEB and double PEB step have thus been applied. First results are interesting though these process variations do not allow fully compensating the image blur induce by the focus scan.

For C040 technology and below, photolithographic depth of focus control and dispersion improvement is essential to secure product functionality. Critical 193nm immersion layers present initial focus process windows close to machine control capability. For previous technologies, the standard scanner sensor (Level sensor - LS) was used to map wafer topology and expose the wafer at the right Focus. Such optical embedded metrology, based on light reflection, suffers from reading issues that cannot be neglected anymore. Metrology errors are correlated to inspected product area for which material types and densities change, and so optical properties are not constant. Various optical phenomena occur across the product field during wafer inspection and have an effect on the quality and position of the reflected light. This can result in incorrect heights being recorded and exposures possibly being done out of focus. Focus inaccuracy associated to aggressive process windows on critical layers will directly impact product realization and therefore functionality and yield. ASML has introduced an air gauge sensor to complement the optical level sensor and lead to optimal topology metrology. The use of this new sensor is managed by the AGILE (Air Gauge Improved process LEveling) application. This measurement with no optical dependency will correct for optical inaccuracy of level sensor, and so improve best focus dispersion across the product. Due to the fact that stack complexity is more and more important through process steps flow, optical perturbation of standard Level sensor metrology is increasing and is becoming maximum for metallization layers. For these reasons AGILE feature implementation was first considered for contact and all metal layers. Another key point is that standard metrology will be sensitive to layer and reticle/product density. The gain of Agile will be enhanced for multiple product contribution mask and for complex System on Chip. Into ST context (High mix logic Fab) in term of product and technology portfolio AGILE corrects for up to 120nm of product topography error on process layer with less than 50nm depth of focus Based on tool functionalities delivered by ASML and on high volume manufacturing requirement, AGILE integration is a real challenge. Regarding ST requirements “Automatic AGILE” functionality developed by ASML was not a turnkey solution and a dedicated functionality was needed. A “ST homemade AGILE integration” has been fully developed and implemented within ASML and ST constraints. This paper describes this integration in our Advanced Process Control platform (APC).

Density multiplication and contact shrinkage of patterned templates by directed self-assembly (DSA) of block copolymers (BCP) stands out as a promising alternative to overcome the limitations of conventional lithography. The main goal of this paper is to investigate the potential of DSA to address contact and via levels patterning with high resolution by performing either CD shrink or contact multiplication. Different DSA processes are benchmarked based on several success criteria such as: CD control, defectivity (missing holes) as well as placement control. More specifically, the methodology employed to measure DSA contact overlay and the impact of process parameters on placement error control is detailed. Using the 300mm pilot line available in LETI and Arkema’s materials, our approach is based on the graphoepitaxy of PS- b -PMMA block copolymers. Our integration scheme, depicted in figure 1, is based on BCP self-assembly inside organic hard mask guiding patterns obtained using 193i nm lithography. The process is monitored at different steps: the generation of guiding patterns, the directed self-assembly of block copolymers and PMMA removal, and finally the transfer of PS patterns into the metallic under layer by plasma etching. Furthermore, several process flows are investigated, either by tuning different material related parameters such as the block copolymer intrinsic period or the interaction with the guiding pattern surface (sidewall and bottom-side affinity). The final lithographic performances are finely optimized as a function of the self-assembly process parameters such as the film thickness and bake (temperature and time). Finally, DSA performances as a function of guiding patterns density are investigated. Thus, for the best integration approach, defect-free isolated and dense patterns for both contact shrink and multiplication (doubling and more) have been achieved on the same processed wafer. These results show that contact hole shrink and multiplication approach using DSA is well compatible with the conventional integration used for CMOS technology.

Directed Self-Assembly (DSA) of Block Copolymers (BCP) is one of the most promising solutions for sub-10 nm nodes. However, some challenges need to be addressed for a complete adoption of DSA in manufacturing such as achieving DSA-friendly design, low defectivity and accurate pattern placement. In this paper, we propose to discuss the DSA integration flows using graphoepitaxy for contact-hole patterning application. DSA process dependence on guiding pattern density has been studied and solved thanks to a new approach called “DSA planarization”. The capabilities of this new approach have been evaluated in terms of defectivity, Critical Dimension (CD) control and uniformity before and after DSA etching transfer.

The formation of air gaps by means of a non-conformal chemical vapor deposition (CVD) on patterned wafers was successfully demonstrated using SiOC (K=2.9) as inter-level metal dielectric. This paper presents the results on physical characterization and electrical performance evaluation of integrated SiOC air gaps in a three-metal level Cu/SiOC interconnect module. The influence of the air gaps shape on parasitic coupling capacitance between copper lines was also discussed in accordance with mask design rules and processing steps.

This paper presents a 14nm technology designed for high speed and energy efficient applications using strain-engineered FDSOI transistors. Compared to the 28nm FDSOI technology, this 14nm FDSOI technology provides 0.55× area scaling and delivers a 30% speed boost at the same power, or a 55% power reduction at the same speed, due to an increase in drive current and low gate-to-drain capacitance. Using forward back bias (FBB) we experimentally demonstrate that the power efficiency of this technology provides an additional 40% dynamic power reduction for ring oscillators working at the same speed. Finally, a full single-port SRAM offering is reported, including an 0.081°m 2 high-density bitcell and two 0.090°m 2 bitcell flavors used to address high performance and low leakage-low Vmin requirements.

T his paper reports on the etch challenges to overcome for the implementation of PS -b-PMMA block c oSRO\PHU¶VDirected Self -Assembly (DSA ) in CMOS via patterning level . Our process is based on a graphoepitaxy approach , employing an industrial PS -b-PMMA block copolymer (BCP) from Arkema with a cylindrical morphology . The process consists in the following step s: a) DSA of block copolymers inside guiding patterns, b) PMMA remov al, c) brush layer opening and finally d ) PS pattern transfer into typical MEOL or BEOL stacks . All results presented here KDYHEHHQSHUIRUPHGRQWKH'6$/HWL¶V PPSLORWOLQH The f irst etch challenge to overcome for BCP transfer involves in removing all PMMA selectively to PS block . In our process baseline, a n acetic acid treatment is carried out to develop PMMA domains . However, this wet development has shown some limitations in te rms of resists compatibility and will not be appropriated for lamellar BCP s. That is why we also investigate the possibility to remove PMMA by only dry etching . In this work the potential of a dry PMMA removal by using CO based chemistries is shown and com pared to wet development . The advantages and limitations of each approach are reported . The second crucial step is the etching of brush layer (PS -r-PMMA ) through a PS mask . We have optimize d this step in order to preserve the PS patterns in terms of CD , holes features and film thickness. Several integrations flow with complex stacks are explored for contact shrink ing by DSA. A study of CD uniformity has been addressed to evaluate the capabilities of DSA approach after graphoepitaxy and after etching . Keyw ords: block copolymer, PS -b-PMMA, contact -hole shrink, PMMA removal, CMOS integration , etching

High density plasma etching processes using halogen based chemistries have been studied for 0.2 μm polysilicon-germanium gate patterning. Bilayer gate stacks consisting of 80 nm polycrystalline Si on 120 nm polycrystalline Si1−xGex (x was varied between 0.55 and 1) were grown on 4.5 nm SiO2 covered 200 mm diameter p-type silicon wafers. The bilayer gates were masked with oxide patterns. The wafers were etched in a low pressure, high density plasma helicon source. Various mixtures, based on Cl2, HBr, and O2 gases, have been used to investigate the etching of the Si/SiGe bilayer gates. The gas mixture and the plasma operating conditions have been optimized to obtain anisotropic etching profiles for features down to 0.2 μm, and to minimize the gate oxide consumption. Real time process control was achieved using HeNe ellipsometry in blanket areas, allowing the SiGe/oxide transition to be easily detected. A two step etching process using a Cl2/O2–He mixture was developed. The first step uses a high energy ion ...

The chemical distribution of oxide-masked polycrystalline Si 0.45 Ge 0.55 structures etched using gas mixtures of Cl 2 , HBr, and O 2 has been investigated by x-ray photoelectron spectroscopy (XPS). The 200 mm diam wafers were etched in a low-pressure, high-density plasma helicon source. The chemical constituents present on the tops, sidewalls, and bottoms of the etched features were determined by XPS. As for polysilicon, a silicon oxide-like film is formed on the sidewalls of the features when etching with HBr/CL/02 and Cl 2 /O 2 plasmas,, whereas there is no germanium oxide-like formation. Using XPS, the silicon oxide-like layer was estimated to be 11 A thick on the sidewalls of the poly Si 0.45 Ge 0.55 , with both mixtures. The thinner oxide-like layer measured on the sidewalls of polycrystalline Si 0.45 Ge 0.55 (11 A) compared to that on the sidewalls of polycrystalline Si (30 A) demonstrates that the oxide-like layer thickness depends on the germanium concentration in the alloy. XPS also shows that by using the Cl 2 /O 2 gas mixture, the germanium of the polycrystalline SiGe sidewalls spontaneously reacts with oxygen to form volatile etching species.

Directed self-assembly (DSA) of block copolymers has shown interesting results for contact hole application, as a vertical interconnection access for CMOS sub-10 nm technology. The control of critical dimension uniformity (CDU), defectivity, and placement error (PE) is challenging and depends on multiple processes and material parameters. This paper reports the work done using the 300-mm pilot line available in materials to integrate the DSA process on contact and via level patterning. In the first part, a reliable methodology for PE measurement is defined. By tuning intrinsic edge detection parameters on standard reference images, the working window is determined. The methodology is then implemented to analyze the experimental data. The impact of the planarization process on PE and the importance of PE as a complement of CDU and hole open yield for process window determination are discussed.

Since 2008, we have been presenting some papers regarding CMOS 45nm logic gate patterning activity to reduce CD dispersion. After a global CD budget evaluation at SPIE08 [1], we have been focusing on Intrafield CD corrections using Dose Mapper™[2]. The story continues and since then we have pursued our intrafield characterisation and focus on ways to get Dose Mapper™ dose recipe created be fore the first silicon is coming. In fact 40nm technology is already more demanding and we must be ready with integrated solutions for 32/28nm node. Global CD budget can be divided in Lot to Lot, Wafer to Wafer, Intra wafer and Intra field component. We won’t talk here about run to run solutions which are put in place for Lot to Lot and Wafer to Wafer. We will emphasize on the intrafield / intrawafer process corrections and outline process compensation control and strategy. A lot of papers regarding intrafield CD compensation are available in the litte rature but they do not necesserally fit logic manufacturing needs or possibilities. We need to put similar solutions in place which are comprehensive and flexible. How can we correct upfront an Etch chambe r CD profile combined with a mask and scanner CD signature? How can we get intrafield map from random logic devices? This is what we will develop in this paper. Keywords: Photolithography, Immersion, Optical CD, Mask, Intrafield, Dose Mapper

H 2 , O 2 , NH 3 and CH 4 in situ post-etching treatments (PET) have been investigated as a solution to prevent the residues formation (TiFx based) on TiN metallic hard mask (MHM) after etching in fluorocarbon based plasmas. The PET impact on the residues growth reduction on the mask and on the porous SiOCH modification is presented and discussed. The compatibility of the different PET is also evaluated for C045 dual damascene level using trench first MHM integration.

A 32 nm node BEOL demonstrator using Trench First Hard Mask (TFHM) architecture is realized. The dual damascene process is performed with ELK dielectric at line and via level and with an adapted metallization in order to meet ITRS specifications. ELK k=2.3 & k=2.2 are studied in a TFHM architecture in order to prove its extendibility to ELK dielectric materials.

The introduction of SiOCH low-k dielectrics in copper interconnects associated to the reduction of the critical dimensions in advanced technology nodes is becoming a major reliability concern. The interconnect realization requires a consequent number of critical process steps [1]. Since porous low-k dielectrics are used as Inter-Metal Dielectric (IMD) each process step can be a source of degradation for the dielectric. This paper describes critical process steps influencing the low-k reliability. All the processes affecting the dielectric's interfaces are also evidenced to degrade the low-k interconnect robustness. Some process examples as the direct chemical and mechanical polishing (CMP), the slurry chemistry and the TaN/Ta barrier etching are details in this paper. Moreover, some process options are given to strongly improve low-k dielectric reliability without degradation of its electrical performances.

This work analyses electromigration and dielectric lifetimes of 45 nm node CMOS interconnects. Reliability mechanisms and failure modes are discussed considering, on one hand, the interconnect materials and processes steps, and on the other hand scaling issues. Robust reliability performance meeting the required products target is actually obtained with process integration schemes used for the 45 nm node thanks to fine optimizations of Cu barriers, Cu filling, and ULK surface quality.

CMOS 45nm technology, and especially the logic gate patterning has led us to hunt for every nanometer we could found to reach aggressive targets in term of overall CD budget. We have presented last year a paper ("Process Control for 45 nm CMOS logic gate patterning " - B. Le Gratiet SPIE2008; 6922-33) showing the evaluation of our process at that time. One of the key item was the intrafield control. Preliminary data were presented regarding intrafield CD corrections using Dose Mapper TM . Since then, more work has been done in this direction and not only for the GATE level. Depending on reticle specification grade, process MEEF and scanner performance, intrafield CD variation can reach quite high CD ranges and become a non negligeable part of the overall budget. Although reticles can achieve very good level of CD uniformity, they all have their own "footprint" which will becomes a systematic error. The key point then is to be able to measure this footprint and correct for it on the wafer. Scanners suppliers provide tools like Dose Mapper TM to modify the intrafield exposure dose profile. Generating and using a proper exposure "subrecipe" requires intrafield in-line control needs on production wafers. This paper present a status of our work on this subject with some results related to global gate CMOS 45nm CD variability improvement including etch process compensation with Dose Mapper.

SiOCH low-k dielectrics introduction in copper interconnects associated to the critical dimensions reduction in sub 45nm technology nodes is a challenge for reliability engineers. Circuit wear-out linked to low-k dielectric breakdown is now becoming a major concern. With the reduction of the line to line spacing, the control of the copper line topology is becoming a first order parameter governing the low-k dielectric reliability. Improving the low-k reliability requires to discriminate each topological effect and quantify its impact on the lifetime at product level. This paper demonstrates the importance of the copper line shape, of the line edge roughness (LER) and of the median line to line spacing variation within the wafer on the low-k dielectrics reliability. Moreover, simple analytical models are described to quantify each effect on the Time-Dependant Dielectric Breakdown (TDDB) and particularly on the final product lifetime. Some advices are given to avoid erroneous lifetime projection.

A full ULK (ultra low-k) integration using TFHM (trench first hard mask) architecture (Hinsiger et al., 2004) is demonstrated in a high density CMOS 45 nm device. 13 nm-pitch metal features have been resolved using a 193 nm immersion hyper-NA (numerical aperture) scanner and an optimized OPC (optical proximity correction) model. RC performance and yield results are presented for a fully-integrated 45 nm ULK backend. An overall speed performance enhancement of >10% has been confirmed within a microprocessor application at the 65 nm technology node when replacing Low-k dielectric (k=2.9) with ULK (k=2.5) material.

Patterning process control has undergone major evolutions over the last few years. Critical dimension, focus, and overlay control require deep insight into process-variability understanding to be properly apprehended. Process setup is a complex engineering challenge. In the era of mid k1 lithography (>0.6), process windows were quite comfortable with respect to tool capabilities, therefore, some sources of variability were, if not ignored, at least considered as negligible. The low k1 patterning (

This paper presents a cost-effective 45-nm technology platform, primarily designed to serve the wireless multimedia and consumer electronics needs. This platform features low power transistors operating at a nominal voltage of 1.1V, an ultra low k dielectric (k~2.5) with up to 9 Cu metal layers and 0.25/0.3/0.37mum2 SRAM cells. This platform also features an optional third gate oxide for either higher speed or active power mitigation. This technology has been developed on the (100)-oriented substrate with a key focus on process simplicity. Transistor improvement relies on mask-free strain engineering techniques along with co-implanted halos and laser anneal. The impact of laser anneal on transistor reliability and mixed-signal capabilities are also examined. Drive current as high as 660/320 muA/mum at 1nA/mum and 1.1V are reported

An enhanced trench first hard mask (TFHM) backend integration architecture has been developed to facilitate straightforward ultra low-k (ULK) material insertion and to enable rapid yield learning at the 65nm technology node. Parametric, yield, reliability, and RC performance data are presented for the fully-integrated, improved TFHM 300mm ULK backend

Semiconductor manufacturers are in the midst of the next technology node C045 (65nm half-pitch) development. The difference this time is that the heavy lifting is being done while swimming. Generally, for the C065 node (hp90), critical layers will be processed using 193-nm scanners with numerical apertures up to 0.85. It is also clear that the capabilities and potential benefits of immersion lithography (at this wavelength and NA) should to be examined, in addition to the development of immersion lithography for the C045 and C032 technology generations. The potential benefits of immersion lithography; increased DOF in the near term and hyper-NA imaging in the next phase, have been widely reported. A strategy of replacing conventional "dry" lithographic process steps with immersion lithographic process steps would allow the benefits of immersion to be realized much earlier. To fully realize this advantage a direct comparison of immersion lithography's benefits and therefore speed learning is needed. However, such an insertion should be "transparent": i.e. the "immersion process" should run with the same reticles (OPC) and resists, as the conventional process. In an effort to gain this knowledge about the immersion processes, we have chosen a path of optimizing and ramping-up the lithographic process for the C065 technology node. In this paper, we report on the compatibility of inserting immersion lithography processes into an established C065 process running in a pilot manufacturing line. We will present an initial assessment of some critical parameters for the implementation of immersion lithography. This assessment includes: OPC compatibility, imaging, process integration, and defectivity all compared to the dry process of record. Finally, conclusions will be made as to the overall readiness of immersion to support C065 node processing in direct transfer from dry and its extendibility to C045. In this work, the C045 technology node (hp65) is the main target vehicle. However, a successful introduction of immersion technology may allow a strategy change complementary with the previous (C065) technology node (i.e. run C065 immersion in production and benefit from larger process windows).

On-going complex integration schemes and developments in processes present significant challenges to lithography in manufacturing advanced semiconductor integrated circuits. Although APC solutions are in place to assist in achieving robust CD control and overlay, there is a great need to increase the 'knowledge' of the system with respect to other contributors impacting the process. The problem becomes more complex in case of an ASIC Prototyping Fab where there is no big runner concept. This leads to the need of a product effect management requirement (Product layout and reticles impact). For this reason, we developed the multivariate R2R controller. This paper discusses the multi-variant methodology and results of a new R2R regulation algorithm in a 65nm node process. Specifically, parameters such as linear combinations of terms, alignment variation for overlay modeled parameters (inter-field / intra-field), CD impacts (reticles, process, tool, STI stack etc) are studied. New solutions for future technology nodes are presented in this paper. It includes for each contributor a multivariate method to assess vector responses and noise contribution. This is being applied on CD and Overlay measurement feedback. For each source of variation (or "Contributor"), the multivariate controller provides the estimated level of compensation requested to meet the target and the level of noise induced on lot processing. At the moment the multivariate R2R controller runs in production. A real evaluation of the existing sources of variations and noise is possible and demonstrated. The result is a significant regulation performance improvement.

Given the much discussed challenges of interconnect scaling at the 65-nm node, the choice of process architecture is a key determinant of performance and extendibility. An alternate trench-first with hardmask integration is described in this work, including subsequent benefits. BEOL design rules are detailed for the 65-nm architecture, supporting both "low-k" and "ultra-low-k" backends, satisfying RC scaling requirements. Electrical parametric performance and yield are presented for a fully-integrated 300mm backend utilizing 65-nm design rules demonstrating the viability of this architecture for the 65-nm node and beyond.

Some of the major limitations of top surface imaging schemes are now well documented: critical dimension (CD) control across the wafer can be a serious issue as well as line edge roughness. A primary focus of our work has been to investigate the performance of the 248 nm bilevel negative tone approach of the chemical vapor deposition photoresist process based on the plasma polymerization of methylsilane. In this article, CD control data within a field and across the wafer are presented. CD control is shown to be very strongly dependent on the uniformity of the development step. The best results are obtained when using straight chlorine for the plasma etch development step.

Top surface imaging processes are considered as attractive schemes for future lithographic processes. A major issue associated with these schemes is the dry development step which implies the obtention of anisotropic resist profiles. This anisotropy is achieve by adding SO2 to O2 gas mixtures. In this work, oxide-masked organic resist features are etched in high density plasma sources using SO2/O2 gas mixtures. The chemical constituents present on the tops, sidewalls, and bottoms of the etched features are determined by quasi in situ x-ray photoelectron spectroscopy (XPS). XPS analyses show that when using SO2/O2 gas mixtures, a thin passivation layer is formed on the sidewalls of the polymer features. This layer is mainly formed by sulfur atoms present on the polymer surface in elemental state or bonded to carbon atoms. This film is thick enough to minimize the spontaneous etching reaction of oxygen atoms with the organic resist. Samples are also analyzed after air exposure in order to determine the air-...

Oxide masked polysilicon/polygermanium 0.18 μm gates were etched in high density plasma sources. Using gas mixtures of Cl2 and HBr with O2 which are commonly used for polysilicon, we observed strong deformation of the poly-Si/poly-Ge gate profiles, whereas perfectly anisotropic etching profiles were obtained for poly-Si gates. A multistep etching recipe was developed allowing anisotropic etching profiles to be obtained while maintaining a good selectivity to the gate oxide when using a Cl2/N2 gas mixture. The chemical constituents present on the tops, sidewalls, and bottoms of the etched features were determined by x-ray photoelectron spectroscopy (XPS). XPS analyses have shown that when using a Cl2/N2 gas mixture, a thin GeNx passivation layer is formed on the sidewalls of the poly-Ge features.