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There is a rapid transition in the semiconductor packaging industry of devices moving toward 40/45-nm extreme low k (ELK) from the development phase into mainstream semiconductor assembly manufacturing. The drive to achieve adoption without major changes to process and equipment infrastructure while meeting the superior yield necessary is high. The main goal of this paper is to share learning's and provide solutions for integration and qualifications of 40/45-nm ELK devices into flip-chip (FC) and wire-bond (WB) package technology. The scope of this paper covers the fine-pitch ball grid array for the WB packages and FC chip-scale package for the FC Devices. The main challenge and focus point for WB 45/40-nm interconnects is on the first bond process. This paper will share some detailed analysis on the following. 1) Characterization for 45 nm ELK ultrafine-pitch. 2) Key factors for good Au ball bond integrity. 3) Recommendations for achieving the required levels of reliability for 45-nm Cu ELK. The challenge of FC Technology today has been changing at a faster rate and more and more adoption has been made from the conventional eutectic solder bumps or high lead solder bumps toward the lead free solder bump mainly due to the Green initiatives. This paper will share analysis on the following areas. 1) Thermo-mechanical simulation on key input factors and its correlation to actual evaluations. 2) Integration of Pb Free ELK bumps with 40-nm ELK technology are various critical processes. 3) Moldable underfill technology for Pb Free + ELK devices. In addition, critical process control is also required at the wafer level process of wafer thinning and dicing, including the need of Laser Grooving will also be covered. more...

HLA™ (Hi-density Leadframe Array) is a new leadframe-based technology that breaks the legacy QFN lead finger constraints and offers a solution to high I/O package requirements in the industry. It can replace many types of leadframe and BGA technologies. As a leadframe-based product, it has limitless design flexibility and allows the designer to design the package around the die. I/O counts of HLA can rival some of the fine pitch BGA products. In the past, in order to gain more leads in a leadframe product, the body size must be increased, which results in longer bond wires and the accompanying issues with wire bond, mold sweep, higher inductance, etc. HLA technology allows routing under the die, so growing the package is no longer necessary. Body sizes in certain lead counts and die sizes of QFN or QFP can generally be reduced by several sizes in an HLA. more...

High performance, multi functional and package miniaturization will be the main driving forces that propel the future trend and development of fully integrated multi silicon dies stack using through silicon via (TSV) packaging technology. This paper serves as an extension of the foregoing paper, where TSV-micro C4 solder interconnect were used and stack up to 4-die compared to the 2-die stack previously demonstrated at ECTC 2010[3]. This study is driven by future requirement for memory dies stacking or multiple devices stacking on a thru silicon interposer (TSI). A TSI enables interconnect pitch matching between a high I/Os top chip and a low cost organic substrate however, extension to 4 die stack reveals many daunting assembly challenges for all backend assembly processes. This paper demonstrates with assistance from finite element analysis, actual process verification and reliability test, the required fundamental changes to material properties, bill of material (BOM) and assembly process manufacturability modification in order to achieve feasible assembly process and reliable performance for 4 thin die stacking to an organic substrate using a 1× solder re-flow process and standard flip chip machine in a mass production scenario. This achievement will further strengthen low cost high volume production capability for thru silicon stacking (TSS). more...

This paper focused on the delamination study of low profile leadframe package with exposed pad (eLQFP). In this type of package, a specification of silver plating area is required for bond pad. With the shrinkage of the non-plating pad area, and because of low adhesion strength between silver and mold compound, the interface of mold compound and die-pad in the silver plating area may potentially delaminate especially after moisture sensitivity level 3 test (MSL3) and IR reflow. The study is to define a design guideline and mold compound selection rule for minimum delamination after MSL3 & IR reflow. Firstly, a safety factor K is defined as delamination guideline. Then the structure parameters were prioritized for their impact to the factor K. Thirdly, a DOE was carried out to study the mold compound property effect on the delamination. Guided by the simulation in structure and mold compound study, a group of test vehicles were designed to validate the reliability. The result shows the well-defined safety factor K was workable for eLQFP failure evaluation. more...