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Majority of practical multivariate statistical analysis and optimizations model interdependence among random variables in terms of the linear correlation. Though linear correlation is simple to use and evaluate, in several cases non-linear dependence between random variables may be too strong to ignore. In this paper, we propose polynomial correlation coefficients as simple measure of multi-variable non-linear dependence and show that the need for modeling non-linear dependence strongly depends on the end function that is to be evaluated from the random variables. Then, we calculate the errors in estimation resulting from assuming independence of components generated by linear de-correlation techniques, such as PCA and ICA. The experimental results show that the error predicted by our method is within 1% error compared to the real simulation of statistical timing and leakage analysis. In order to deal with non-linear dependence, we further develop a target-function-driven component analysis algorithm (FCA) to minimize the error caused by ignoring high order dependence. We apply FCA to statistical leakage power analysis and SRAM cell noise margin variation analysis. Experimental results show that the proposed FCA method is more accurate compared to the traditional PCA or ICA.

Three-dimensional (3-D) routing is an important step in deep submicrometer very large-scale integrated design. Given a 3-D grid graph and a set of two-terminal nets to be routed, we propose a probabilistic model to calculate the routing density (congestion) on each edge of the grid graph. The routing density provides a direct congestion estimation. Our experimental results demonstrate the effectiveness of the method on routing benchmarks. Index Terms--Estimation, probabilistic methods, routing.

Short-loop process monitoring structures (usually simple device I-V, C-V measurements made after M1 fabrication) are commonly put in wafer scribelines. These test structures are almost always design independent and measured or monitored by the foundry to keep track of process deviations. We propose a design-dependent process monitoring strategy that can accurately predict design performance based on Ieff-based delay and Ioff-based leakage power estimates. Further, we use the predicted delay and power for early yield estimation to: 1) prune bad wafers to save test and back-end manufacturing costs, and 2) prune bad dies to save testing costs. Combining chip pruning with wafer pruning, we can reduce the cost per good chip by up to 13%. Such design-dependent process monitoring can help reduce process optimization effort, and enable quicker yield ramp besides saving testing and manufacturing costs. [ABSTRACT FROM PUBLISHER]

The most challenging problem in the current block-based statistical static timing analysis (SSTA) is how to handle the max operation efficiently and accurately. Existing SSTA techniques suffer from limited modeling capability by using a linear delay model with Gaussian distribution, or have scalability problems due to expensive operations involved to handle non-Gaussian variation sources or nonlinear delays. To overcome these limitations, we propose efficient algorithms to handle the max operation in SSTA with both quadratic delay dependency and non-Gaussian variation sources simultaneously. Based on such algorithms, we develop an SSTA flow with quadratic delay model and non-Gaussian variation sources. All the atomic operations, max and add, are calculated efficiently via either closed-form formulas or low dimension (at most 2-D) lookup tables. We prove that the complexity of our algorithm is linear in both variation sources and circuit sizes, hence our algorithm scales well for large designs. Compared to Monte Carlo simulation for non-Gaussian variation sources and nonlinear delay models, our approach predicts the mean, standard deviation and 95% percentile point with less than 2% error, and the skewness with less than 10% error. [ABSTRACT FROM PUBLISHER]

Today's very deep submicron IC technology enables high-performance analog and digital applications to be integrated on a single piece of silicon. For this effort, a design of 2.5 giga sample per second (GSPS) receiver-on-a-chip (ROC) is presented. For our design, we take advantage of a compensation technique to reduce spurs and improve instantaneous dynamic range. A major goal is to produce a low-cost, small, and lightweight, and low-power ROC. Our design will cover a 1-GHz bandwidth (125-1125 MHz), and it will correctly process two simultaneous signals by detecting their frequency, pulsewidth (PW), and time of arrival (TOA). The single or dual signal, spur-free dynamic ranges and two signal instantaneous dynamic ranges of our design are high. The minimum frequency separation of two signals is 10 MHz (one channel width), and the maximum amplitude separation (dynamic range) of two signals is 18 dB with the second signal false alarm less than 1%. [ABSTRACT FROM AUTHOR]