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This paper presents two novel current-mode Full Adders based on Carbon Nanotube FET (CNFET). They comprise of three main parts: current-to-voltage converter, threshold detector and voltage-to-current converter. While other designs in the literature use either inverter or current source for detecting threshold, the new designs are based on a heuristic usage of an Ultra Low-Power Diode (ULPD) as voltage regulator. The use of diode does not lengthen the critical path and thereby ensuring high-speed operation. It does not increase power consumption significantly either. Simulation results by HSPICE and 32nm CNFET technology file demonstrate at least 19% higher performance in terms of energy consumption for the second proposed Full Adder compared to other traditional and state-of-the-art current-mode and mixed-mode designs. [ABSTRACT FROM AUTHOR]

This paper presents current-mode multi-input m:3 (4 ≤ m ≤ 7) counters based on carbon nanotube FET (CNTFET). Two different approaches are considered for these designs. In the first approach, a current mode m:3 (4 ≤ m ≤ 7) counter is achieved by means of current-mirrors in the output paths. The second proposed current-mode m:3 (4 ≤ m ≤ 7) counter is designed without requiring current-mirrors. This leads to lower number of transistors and lower power dissipation in comparison with the first approach. All of the designs are simulated using the Stanford CNTFET HSPICE model at 32 nm feature size. The results indicate that the second proposed designs are consistently faster and consume lower power than the first designs. Therefore, our PDP figure is improved by 35%, 30%, 36% and 26% as compared to those of current-mode logic (CML) counter 4:3, CML counter 5:3, CML counter 6:3 and CML counter 7:3, respectively. [ABSTRACT FROM AUTHOR]

In the present technology development billions of transistors are fabricated on a single chip, which improves the performance of circuits in terms of high data transmission speed and power consumption. This requirement of data transmission speed is achieved with the help of high-speed transceivers. In this paper, we present a high-speed asynchronous wave-pipelined serializer and deserializer (SerDes) transceiver implemented using current-mode logic (CML). This asynchronous transceiver circuit does not require a clock and therefore it saves large amount of power which is consumed in the phase locked loop (PLL) and frequency synthesizer circuits. Further, the proposed design is built using CML which saves more power. CML circuit operates at relatively higher speed as compared to CMOS circuits which helps the circuit to operate at higher data rate. Compared to conventional CML latch, a novel CML latch is proposed in our design to increase the speed. The circuit is implemented in standard CMOS 65-nm technology. The total power consumed by the serializer and deserializer is 9.32 mW, which is very less as compared to published related works. The proposed asynchronous SerDes transceiver operates at 18.1-Gbps data transmission rate with low power dissipation. [ABSTRACT FROM AUTHOR]

An 80-Gb/s $2^{15}-1$ pseudorandom binary sequence (PRBS) generator suitable for testing binary communication systems is presented. Implemented in a 130-nm SiGe process, the circuit is optimized for low power dissipation. For the core functionality, an energy efficiency of 1 pJ/bit is achieved, which is one of the best values among comparable published designs. In addition, the improvement of the output signal in time domain and frequency domain is targeted. The key factors affecting an ideal PRBS spectrum are identified and addressed from the system and circuit point of view. This results in spur suppression of higher than 40 dB, which is 15 dB better than previously reported works exceeding 40 Gb/s. As an output driver, a modified Cherry–Hooper amplifier is chosen. A parametrized design methodology for obtaining Bessel response is introduced and the amplifier is optimized for low power operation. Measurement results show a single-ended output signal with over 300-mV eye opening, 0.6-ps rms jitter, and a signal-to-noise ratio better than 10.5 at 80 Gb/s, which is the best-in-class output eye diagram for a PRBS generator, to the best of our knowledge. [ABSTRACT FROM AUTHOR]

Optical links are rapidly becoming pervasive in the readout chains of particle physics detector systems. Silicon photonics (SiPh) stands as an attractive candidate to sustain the radiation levels foreseen in the next-generation experiments, while guaranteeing, at the same time, multi-Gb/s and energy-efficient data transmission. Integrated electronic drivers are needed to enable SiPh modulators’ deployment in compact on-detector front-end modules. A current-mode logic-based driver harnessing a pseudo-differential output stage is proposed in this work to drive different types of SiPh devices by means of the same circuit topology. The proposed driver, realized in a 65 nm bulk technology and already tested to behave properly up to an 8 MGy total ionizing dose, is hybridly integrated in this work with a lumped-element Mach–Zehnder modulator (MZM) and a ring modulator (RM), both fabricated in a 130 nm silicon-on-insulator (SOI) process. Bit-error-rate (BER) performances confirm the applicability of the selected architecture to either differential and single-ended loads. A 5 Gb/s data rate, in line with the current high energy physics requirements, is achieved in the RM case, while a packaging-related performance degradation is captured in the MZM-based system, confirming the importance of interconnection modeling.

Abstract A new current-mode Wheatstone bridge (CMWB) using a new fully differential operational transresistance amplifier (FDOTRA) is presented in this paper. This proposed FDOTRA is an active element for the proposed CMWB and has the advantages of low input and output impedances, input voltage calibration, high transimpedance (R m), large input range, and wide bandwidth. The proposed CMWB uses only one active component FDOTRA and four resistors without degrading CMWB performance. The proposed CMWB has a simple structure, high precision, wide range, small volume, and low cost. Therefore, the advantages of the proposed CMWB are twofold. Firstly, it reduces the number of sensing passive and active elements. Secondly, the proposed CMWB circuit offers a significant improvement in accuracy compared to other CMWB integrated circuit (IC). The proposed CMWB has been analyzed, simulated, and implemented. The proposed FDOTRA has been fabricated with TSMC 0.35 μm 2P4M CMOS processes. Its supply voltages are ±1.65 V. The open-loop gain and 3-dB bandwidth of the proposed FDOTRA are 69.2 dB and 16 MHz, respectively. The open-loop gain and 3-dB bandwidth of the FDOTRA based CMWB are 24.6 dB and 16 MHz, respectively. The experimental results show that the precision of the FDOTRA based CMWB is 92.4%. [ABSTRACT FROM AUTHOR]

Multi valley current mode pulse train (MVC-PT) control technology can completely eliminate the low-frequency oscillation phenomenon of DC-DC switching converters operated in continuous conduction mode (CCM). However, this method needs to increase the number of preset value to broaden the output power range, which will increase the complexity and cost of the controller, and reduce the robustness of the system. Meanwhile, the output voltage ripple is uncontrollable and varied with the changes of the load. In this paper, a novel sliding valley current mode PT (SVC-PT) control technique is proposed to solve the above-mentioned problem. The SVC-PT operating principle and the deficiency of MVC-PT method are analysed in details. The approximate discrete-time models of SVC-PT and MVC-PT controlled switching DC-DC converters are constructed and compared. The comparison results verify that the proposed control method can thoroughly lessen the restriction of the controller on the output power range. Moreover, the control circuit is simplified and the output voltage ripple can be controlled. Finally, the simulation and experimental results are present to prove the feasibility and scientific of SVC-PT control technology. [ABSTRACT FROM AUTHOR]

Radio frequency (RF) analog applications present an interesting opportunity for carbon nanotube (CNT)-based electronics. Extrinsic peak operating frequencies of up to 40 GHz for CNT field-effect transistors manufactured on wafer scale employing very moderate dimensions have been already demonstrated. However, as in any emergent technology, variability of the fabricated devices is significant. Therefore, predictions about the behavior of benchmark circuits at the process corners are required to further stimulate complex RF design and fabrication. We report here on the projected tolerance of a current-mode logic (CML) buffer/inverter designed for 2.4 GHz (5 Gb/s), 1.8-V supply voltage, 1.8-mA tail current, and a 600-mV voltage swing. The single CML stage is very robust against variations in CNT density but vulnerable to source-drain shorts introduced by metallic tubes in the channel. A corresponding five-stage CML ring oscillator shows considerably reduced output voltage swing beyond two percent metallic tube fraction indicating the importance of metallic tube reduction by technology dependent strategies like presorting, post-elimination, or type-selective growth. [ABSTRACT FROM PUBLISHER]

Unlike the conventional pulse width modulation control, a unique current-mode pulse train (CMPT) control technique presents a different nonlinear dynamics associated with the power electronics system. The quadratic boost converter in discontinuous conduction mode (DCM) is examined under CMPT control. The control performance of the system is studied by analyzing the combination of high-power control pulse PH and low-power control pulse PL of a control pulse repetition cycle in regulating the output voltage. The computer simulation is accomplished to capture the gist of the system dynamics revealing the periodic transition manifested due to border collision bifurcation under the influence of the variation in input voltage and load resistance. The stability of the system is assessed with the evidence of loci of eigenvalues from two-dimensional discrete-time model and maximal Lyapunov exponents obtained using QR decomposition algorithm. An experimental setup is also developed to verify the simulated and analytical dynamics witnessed. [ABSTRACT FROM AUTHOR]

The conventional slope compensations for current mode controls do not take all the parameters’ changes into account, so the variations on small-signal transfer functions limit the voltage loop bandwidth (BW). In order to optimize the dynamic performance of current-mode control, this letter proposes a universal auto-tuning technique for external ramp slope based on the sensed slope of current feedback signal. The tuning mechanism keeps the quality factor of the double poles unchanged over the duty cycle variation, inductor tolerance, sensing element variation, and topology change, thus a consistent wide BW control is achieved without the limitation from the corner cases. Simple digital and analog implementations are proposed to realize the auto-tuning concept. This method is applicable to digital and analog current-mode controllers with peak current mode, valley current mode, and average current mode operations. The effectiveness of the proposed method is verified by simulation and experimental results. [ABSTRACT FROM AUTHOR]

This paper presents the design of a novel low-voltage high-speed D-latch circuit suitable for nanometer CMOS technologies. The proposed topology is compared against the low-voltage triple-tail D-latch and its advantages are demonstrated both by simulations, under different performance/power consumption tradeoffs with a 40-nm CMOS technology, and theoretically, thanks to a simple model of the propagation delay derived for both low-voltage topologies. In order to further demonstrate the advantages of the proposed topology, it has also been used to design a D flip-flop (DFF), where thanks to the feature to need just 1 clock differential pair; a further speed improvement is achieved over the conventional triple-tail topology. Indeed, by comparing a two-stage frequency divider designed using both the triple-tail DFF and the proposed folded DFF, a 54% improvement in the maximum operating frequency is found when using the proposed folded DFF. [ABSTRACT FROM AUTHOR]

The causes of supply induced noise are investigated and a circuit technique that reduces the supply sensitivity of CML ring oscillator is presented. This technique applies a current bias circuit with negative supply sensitivity to compensate the intrinsic positive sensitivity of VCO and alleviate the impact of supply voltage fluctuation. A prototype chip is fabricated in a 180 nm CMOS process to prove its rejection of supply noise. [ABSTRACT FROM AUTHOR]

This study presents a model following average-current-mode (MFACM) control using a 1/³√ compensator to improve robustness and dynamic response for multiphase boost converters. The proposed 1/³√ compensator can maintain a constant phase boost of about 60° over two decades, which is attractive from the point of view of stability design when phase margin, gain margin, delay margin and modulus margin are taken into consideration. In addition, the MFACM control is shown to elevate perturbation rejection ability of converters by reducing closed-loop output impedance and closed-loop audio susceptibility, relative to traditional average-current-mode control methods with the almost same crossover frequency. Computer simulations and experimental results using a three-phase interleaved boost converter are shown close agreement between modelled estimates and measured values. [ABSTRACT FROM AUTHOR]

A novel current-mode (CM) universal filter configuration composed of five plus-type second-generation current conveyors (CCII+s) as active components besides three resistors and three grounded capacitors as passive elements is proposed in this paper. The proposed filter can simultaneously provide high-pass, band-pass and low-pass responses. Also, it can realize all-pass and notch responses with interconnection of convenient output currents. It can be cascaded with other CM ones easily because it has low input and high output impedances. It offers orthogonal control of angular resonance frequency and quality factor. An electronically tunable universal filter can be easily obtained if plus-type current controlled current conveyors are replaced instead of each of the five CCII+s and all the three resistors are removed. Nevertheless, it needs a single passive element matching constraint for notch and all-pass filter responses. Some simulation and experimental test results are included to confirm the theory. [ABSTRACT FROM AUTHOR]

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High speed and low power are the main challenges in modern VLSI design. The proposed paper presents swift frequency divider circuit using MCML (MOS Current Mode Logic). The divider operates up to 60GHZ clock frequency. The implementation is carried by using 45nm cadence virtuoso tool. The presented logic consumes 2.5mW from 1.2V supply. The phase noise of the proposed frequency divider is 150dBc/Hz at 60GHz offset. [ABSTRACT FROM AUTHOR]

This paper presents several design techniques to widen the operating frequency range and increase the locking range of dynamic current-mode latch-based inductor-less millimeter-wave frequency dividers. A self-calibration technique is introduced to guarantee frequency locking over a wide frequency range with low-input amplitude and over process, voltage, and temperature variations, thereby optimizing power consumption and ensuring robustness. Three divide-by-four prototypes incorporating the aforementioned techniques are designed to cover a frequency range exceeding 16–67 GHz. Fabricated in a 65-nm CMOS technology, the prototypes achieve min-average-max increases of 10%–47.5%–121.4% in fractional bandwidth over the state of the art. The first and third prototypes consume 3.7/6.2 mA (min/max) from a 1-V supply and achieve a figure of merit of 4.1/7.15 GHz/mW (min/max), while the second prototype consumes 3.9/6.7 mA (min/max) from a 1.1-V supply and achieves a figure of merit of 3/6.98 GHz/mW (min/max). The prototypes occupy the active areas of 11 \times 42/11 \times 53~\mu \textm^2 (min/max). Finally, with the self-calibration scheme, the dividers operate with input power less than −10 dBm, supply voltage variation of ±100 mV. [ABSTRACT FROM PUBLISHER]

A novel unified model, for conventional copper and futuristic multilayer graphene nanoribbon (MLGNR) interconnects, based on a finite-difference time-domain (FDTD) technique has been proposed in this paper. The performance of quasi-transverse electromagnetic model of interconnects has been exhaustively analyzed for both voltage-mode signaling (VMS) and current-mode signaling (CMS) schemes. The effect of variations in edge roughness and dopant dependent Fermi energy in MLGNR interconnects has been examined. The crosstalk and coupling effects in interconnects have been investigated by incorporating capacitive and inductive interconnect parasitic elements. From the results carried out for 32-nm technology node, it has been observed that for similar dimensions and operating conditions, MLGNR interconnects show a significant performance improvement over the copper interconnects. The results also show that the CMS scheme outperforms VMS scheme at global wire lengths and is very suitable for state-of-the-art chip applications. The proposed model results are in close propinquity with the SPICE results. Furthermore, the FDTD-based model is computationally efficient compared to SPICE. [ABSTRACT FROM PUBLISHER]

This paper presents a dual band Digitally-Controlled-Oscillator (DCO) based on Ring-Oscillators (RO) topology with differential input/output at 1.45 GHz is proposed. The circuit has two frequency band which switches by a digital mode bit. Switching between two bands of DCO, will change delay path and power consumption during the run time. A new Source-Coupled-Logic (SCL) based reconfigurable delay element with Schmitt-Trigger (ST) characteristic is used in each stage and 6 bits digital code control their current tails. Power consumption profile with frequency in each band has a steady regime. The proposed designs are fully differential, which is appropriate for low jitter high performance applications. The proposed DCO is simulated by spice with CMOS standard 0.18 µm @ 1.8 v supply. The frequency, power consumption and jitter in lower band are 455.2 MHz to 505.1 MHz, 1.98 mW (at 455 MHz), 6.04 ps (at 505.1 MHz) and for upper band are from 1.39 MHz to 1.45 MHz, 9.7 mW (at 1.39 GHz) and 3.48 ps (at 1.45 MHz), sequentially. In this paper also circuit analysis of proposed DCO, delay calculation and comparison and analytical equation for frequency bands are obtained. Also, Monte Carlo and PVT test shows acceptable frequency tolerance. [ABSTRACT FROM AUTHOR]

This paper presents dynamic positive feedback source-coupled logic (D-PFSCL) style which is derived from positive feedback source-coupled logic (PFSCL). The proposed logic style uses dynamic current source in contrast to constant current source of PFSCL to attain lower power consumption. Two techniques for D-PFSCL style-based multistage applications are suggested. Several D-PFSCL gates are simulated and compared with the respective PFSCL counterparts through SPICE simulations by using Taiwan semiconductor manufacturing company 0.18 µm CMOS technology parameters. A maximum power reduction of 84% is achieved for D-PFSCL gates. The effect of process variation on the power consumption of the D-PFSCL gates shows a maximum variation factor of 1.5 between the best and the worst cases. [ABSTRACT FROM PUBLISHER]

Alternative energy source systems such as solar-cells or photovoltaic systems become more and more popular. This paper deals with the utilization of three-phase step up converter with magnetically uncoupled smoothing inductors for control of voltage and power transfer in alternative energy sources, or between dc to dc, dc to ac and ac to dc systems using peak current control mode technique. The converter is studied, simulated and investigated not only in Matlab but also in the environment of Simplorer to guarantee that the simulation results are accurate and that the voltage produced at the output of alternative energy sources is stepped up and hence their usual low efficiency is greatly enhanced. The paper shows that multichannel converter with uncoupled smoothing inductors has inherent advantages as compared to the fundamental converter such as increasing the output power and filtering out the high harmonic content from the output. Moreover, the paper deals with using compensated proportional integral controller (PI) controllers based on the pulse width modulation constant frequency modulation technique along with current-mode control method. The simulation results show that current-mode control technique with such compensated PI controllers provides good current and voltage regulation of such converter that could operate efficiently even under nonlinear conditions. [ABSTRACT FROM AUTHOR]

In recent technology nodes, a timing-error issue due to particle strike into semiconductor materials is getting critical. This paper evaluates a soft-delay-error (SDE) effect due to particle strike for soft-error tolerant content-addressable memories (CAMs). The SDE is that a particle strike into semiconductor materials induces a transient pulse signal, causing a delay variation and a timing error of an integrated circuit. The delay variation is evaluated using a charge-injection model at a transistor level for two different CAMs. One of the CAMs is a traditional 9-transistor-cell based CAM and the other is a magnetictunnel- junction (MTJ)/MOS hybrid cell based CAM that operates based on a multiple-valued current-mode logic. These two CAMs are simulated using a SPICE simulator that can handle both transistors and MTJ devices in a 90nm CMOS/100nm MTJ technology. Based on the simulation results, circuit architectures and design parameters are discussed in order to design soft-error tolerant CAMs. [ABSTRACT FROM AUTHOR]

In this article, a new current-mode, accurate, and fully programmable Interval Type-2 (IT2) membership function generator (MFG) in 0.18 m CMOS technology is presented. This IT2 fuzzifier is based on a Type-1(T1) fuzzifier that uses a new method for slope tuning. The proposed slope tuning method, leads to smaller active area and also significantly smaller total die area by reducing the number of required pins in comparison with previous methods. Small area, low power consumption, and especially suitable programming method, makes the proposed IT2 MFG suitable for fuzzifier block of general-purpose Fuzzy Logic Controllers (FLCs). The proposed IT2 MFG has an average power consumption of 570Wand has an area of 0.0183mm2. Simulation results using HSPICE in a typical 0.18 m CMOS technology are presented to analyze the behavior of designed circuits. [ABSTRACT FROM AUTHOR]

This paper presents a complete 50–64 Gb/s serializing transmitter including a 4-tap equalizer. An LC-based FFE structure is proposed. The FFE improves the bandwidth of the delay line and the output combiner by applying the design methodology of LC-ladder filters. Proper arrangement of the output combiner reduces the required number of inductors and hence reduces the area. In addition, a novel 4:1 multiplexer (MUX) is used as the final stage of the serializer to reduce power. Designed and fabricated in 65 nm CMOS technology, the transmitter achieves a maximum data rate of 64.5 Gb/s with an energy efficiency of 3.1 pJ/bit. [ABSTRACT FROM PUBLISHER]

The average-current-controlled boost power factor correction converter may operate in all-continuous current mode (CCM), part-CCM/discontinuous current mode (DCM), or all-DCM mode in a half line cycle under different input voltage and load conditions, and the conducted electromagnetic interference (EMI) spectrum of the converter exhibits differences in these operation modes. In this paper, by analyzing the characteristic of the harmonics of the drain-to-source voltage of the power switch, the characteristics of the common-mode and differential-mode noise of the converter are revealed in different operation modes. The analyzed results can be used to guide the EMI filter design for the converter and ensure the conducted EMI satisfying the standard under all working conditions. [ABSTRACT FROM PUBLISHER]