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In this paper, a low-cost and low-leakage gate-first high- \(k\) metal-gate CMOS integration compatible with the high thermal budget used in a 2× node dynamic random access memory process flow is reported. The metal inserted polysilicon stack is based on HfO2 coupled with Al2O3 capping for pMOS devices, and with a TiN/Mg/TiN stack together with As ion implantation for nMOS. It is demonstrated that n and pMOS performance of 400 and 200 \(\mu \) A/ \(\mu \) m can be obtained for an OFF-state current of \(10^{-10}\) A/ \(\mu \) m, while maintaining gate and junction leakages compatible with low-power applications. Reliability and matching properties are aligned with logic gate-stacks, and the proposed solution is outperforming the La-cap-based solutions in terms of thermal stability. [ABSTRACT FROM AUTHOR]

Deals with the use of complementary metal oxide semiconductors (CMOS) technology. Details on the efforts of semiconductor companies to improve the performance of CMOS; Trends in the electronics market; Information on gate-architecture engineering; How to manage low threshold voltage values; Application of silicon on insulators in managing low threshold voltage; Impacts of gate-dielectric engineering on terabit-class devices.

Leakage currents as low as \(10^{\mathrm {\mathbf {-7}}}\) A/cm \(^{\mathrm {\mathbf {2}}}\) at both 1 V and −1 V top electrode bias in the sub-0.4-nm equivalent SiO2 thickness range are demonstrated in Ru/SrTiOx/Ru metal-insulator–metal capacitors in which the 8.5-nm SrTiOx layer is deposited by atomic layer deposition. The top electrode material and deposition technique as well as the postdeposition anneal are crucial parameters to control the leakage, not only at negative, but also at positive top electrode bias. [ABSTRACT FROM AUTHOR]