78 results on '"Calazans, Ney L. V."'
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2. A differential IR-UWB transmitter using PAM modulation with adaptive PSD
3. A Complementary Survey of Radiation-Induced Soft Error Research: Facilities, Particles, Devices and Trends.
4. A new local clock generator for globally asynchronous locally synchronous MPSoCs
5. Modeling the Traffic Effect for the Application Cores Mapping Problem onto NoCs
6. Mitigating Asynchronous QDI Drawbacks on MAC Operators with Approximate Multipliers
7. Asynchronous Circuit Principles and a Survey of Associated Design Tools.
8. Quasi Delay Insensitive FIFOs: Design Choices Exploration and Comparison
9. A GALS Pipeline DES Architecture to Increase Robustness against CPA and CEMA Attacks
10. Towards an Integrated Software Development Environment for Robotic Applications in MPSoCs with Support for Energy Estimations
11. Leveraging QDI Robustness to Simplify the Design of IoT Circuits
12. A Frontend using Traditional EDA Tools for the Pulsar QDI Design Flow
13. Robust and Energy-Efficient Hardware: The Case for Asynchronous Design.
14. Pulsar: Constraining QDI Circuits Cycle Time Using Traditional EDA Tools
15. Asynchronous Quasi-Random Number Generator: Taking Advantage of PVT Variations
16. NCL Synthesis With Conventional EDA Tools: Technology Mapping and Optimization
17. Hardening C-elements against metastability
18. Go functional model for a RISC-V asynchronous organisation — ARV
19. XGT4: An industrial grade, open source tester for multi-gigabit networks
20. Sleep convention logic isochronic fork
21. A comparison of asynchronous QDI templates using static logic
22. ASCEnD-FreePDK45: An open source standard cell library for asynchronous design
23. A Fine-Grain, Uniform, Energy-Efficient Delay Element for 2-Phase Bundled-Data Circuits
24. A Low-Power Low-Area Error-Detecting Latch for Resilient Architectures in 28-nm FDSOI
25. Testable MUTEX Design
26. Analysis and Design of Delay Lines for Dynamic Voltage Scaling Applications
27. The HF-RISC processor: Performance assessment
28. SDDS-NCL Design
29. A Fine-Grained, Uniform, Energy-Efficient Delay Element for FD-SOI Technologies
30. TDTB error detecting latches: Timing violation sensitivity analysis and optimization
31. A digitally controlled oscillator for fine-grained local clock generators in MPSoCs
32. Advances on the state of the art in QDI design
33. Modeling the Traffic Effect for the Application Cores Mapping Problem onto NoCs
34. Tradeoffs between RTO and RTZ in WCHB QDI asynchronous design
35. Automatic layout synthesis with ASTRAN applied to asynchronous cells
36. A flexible soft IP core for standard implementations of elliptic curve cryptography in hardware
37. BaBaNoC: An asynchronous network-on-chip described in Balsa
38. Charge sharing aware NCL gates design
39. SDDS-NCL design: Analysis of supply voltage scaling.
40. NCL+: Return-to-one Null Convention Logic
41. Return-to-One DIMS logic on 4-phase m-of-n asynchronous circuits
42. Electrical characterization of a C-Element with LiChEn
43. A spectrum of MPSoC models for design space exploration and its use
44. Return-to-one protocol for reducing static power in C-elements of QDI circuits employing m-of-n codes
45. Configurable platform for IC combined tests of total-ionizing dose radiation and electromagnetic immunity
46. Hermes-AA: A 65nm asynchronous NoC router with adaptive routing
47. Floating Point Hardware for Embedded Processors in FPGAs: Design Space Exploration for Performance and Area
48. HeMPS - a framework for NoC-based MPSoC generation
49. Evaluation of Algorithms for Low Energy Mapping onto NoCs
50. Design of NCL gates with the ASCEnD flow.
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