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In the span of four decades, quantum computation has evolved from an intellectual curiosity to a potentially realizable technology. Today, small-scale demonstrations have become possible for quantum algorithmic primitives on hundreds of physical qubits and proof-of-principle error-correction on a single logical qubit. Nevertheless, despite significant progress and excitement, the path toward a full-stack scalable technology is largely unknown. There are significant outstanding quantum hardware, fabrication, software architecture, and algorithmic challenges that are either unresolved or overlooked. These issues could seriously undermine the arrival of utility-scale quantum computers for the foreseeable future. Here, we provide a comprehensive review of these scaling challenges. We show how the road to scaling could be paved by adopting existing semiconductor technology to build much higher-quality qubits, employing system engineering approaches, and performing distributed quantum computation within heterogeneous high-performance computing infrastructures. These opportunities for research and development could unlock certain promising applications, in particular, efficient quantum simulation/learning of quantum data generated by natural or engineered quantum systems. To estimate the true cost of such promises, we provide a detailed resource and sensitivity analysis for classically hard quantum chemistry calculations on surface-code error-corrected quantum computers given current, target, and desired hardware specifications based on superconducting qubits, accounting for a realistic distribution of errors. Furthermore, we argue that, to tackle industry-scale classical optimization and machine learning problems in a cost-effective manner, distributed quantum-assisted probabilistic computing with custom-designed accelerators should be considered as a complementary path toward scalability., Comment: 50 pages, 42 figures

Ising machines, hardware accelerators for combinatorial optimization and probabilistic sampling problems, have gained significant interest recently. A key element is stochasticity, which enables a wide exploration of configurations, thereby helping avoid local minima. Here, we refine the previously proposed concept of coupled chaotic bits (c-bits) that operate without explicit stochasticity. We show that augmenting chaotic bits with stochasticity enhances performance in combinatorial optimization, achieving algorithmic scaling comparable to probabilistic bits (p-bits). We first demonstrate that c-bits follow the quantum Boltzmann law in a 1D transverse field Ising model. We then show that c-bits exhibit critical dynamics similar to stochastic p-bits in 2D Ising and 3D spin glass models, with promising potential to solve challenging optimization problems. Finally, we propose a noise-augmented version of coupled c-bits via the adaptive parallel tempering algorithm (APT). Our noise-augmented c-bit algorithm outperforms fully deterministic c-bits running versions of the simulated annealing algorithm. Other analog Ising machines with coupled oscillators could draw inspiration from the proposed algorithm. Running replicas at constant temperature eliminates the need for global modulation of coupling strengths. Mixing stochasticity with deterministic c-bits creates a powerful hybrid computing scheme that can bring benefits in scaled, asynchronous, and massively parallel hardware implementations.

Stochastic magnetic tunnel junctions (s-MTJ) is a promising component of probabilistic bit (p-bit), which plays a pivotal role in probabilistic computers. For a standard cell structure of the p-bit, s-MTJ is desired to be insensitive to voltage across the junction over several hundred millivolts. In conventional s-MTJs with a reference layer having a fixed magnetization direction, however, the stochastic output significantly varies with the voltage due to spin-transfer torque (STT) acting on the stochastic free layer. In this work, we study a s-MTJ with a "double-free-layer" design theoretically proposed earlier, in which the fixed reference layer of the conventional structure is replaced by another stochastic free layer, effectively mitigating the influence of STT on the stochastic output. We show that the key device property characterized by the ratio of relaxation times between the high- and low-resistance states is one to two orders of magnitude less sensitive to bias voltage variations compared to conventional s-MTJs when the top and bottom free layers are designed to possess the same effective thickness. This work opens a pathway for reliable, nanosecond-operation, high-output, and scalable spintronics-based p-bits.

An emerging paradigm in modern electronics is that of CMOS + $\sf X$ requiring the integration of standard CMOS technology with novel materials and technologies denoted by $\sf X$. In this context, a crucial challenge is to develop accurate circuit models for $\sf X$ that are compatible with standard models for CMOS-based circuits and systems. In this perspective, we present physics-based, experimentally benchmarked modular circuit models that can be used to evaluate a class of CMOS + $\sf X$ systems, where $\sf X$ denotes magnetic and spintronic materials and phenomena. This class of materials is particularly challenging because they go beyond conventional charge-based phenomena and involve the spin degree of freedom which involves non-trivial quantum effects. Starting from density matrices $-$ the central quantity in quantum transport $-$ using well-defined approximations, it is possible to obtain spin-circuits that generalize ordinary circuit theory to 4-component currents and voltages (1 for charge and 3 for spin). With step-by-step examples that progressively become more complex, we illustrate how the spin-circuit approach can be used to start from the physics of magnetism and spintronics to enable accurate system-level evaluations. We believe the core approach can be extended to include other quantum degrees of freedom like valley and pseudospins starting from corresponding density matrices.

Despite their appeal as physics-inspired, energy-based and generative nature, general Boltzmann Machines (BM) are considered intractable to train. This belief led to simplified models of BMs with restricted intralayer connections or layer-by-layer training of deep BMs. Recent developments in domain-specific hardware -- specifically probabilistic computers (p-computer) with probabilistic bits (p-bit) -- may change established wisdom on the tractability of deep BMs. In this paper, we show that deep and unrestricted BMs can be trained using p-computers generating hundreds of billions of Markov Chain Monte Carlo (MCMC) samples per second, on sparse networks developed originally for use in D-Wave's annealers. To maximize the efficiency of learning the p-computer, we introduce two families of Mean-Field Theory assisted learning algorithms, or xMFTs (x = Naive and Hierarchical). The xMFTs are used to estimate the averages and correlations during the positive phase of the contrastive divergence (CD) algorithm and our custom-designed p-computer is used to estimate the averages and correlations in the negative phase. A custom Field-Programmable-Gate Array (FPGA) emulation of the p-computer architecture takes up to 45 billion flips per second, allowing the implementation of CD-$n$ where $n$ can be of the order of millions, unlike RBMs where $n$ is typically 1 or 2. Experiments on the full MNIST dataset with the combined algorithm show that the positive phase can be efficiently computed by xMFTs without much degradation when the negative phase is computed by the p-computer. Our algorithm can be used in other scalable Ising machines and its variants can be used to train BMs, previously thought to be intractable.

We show that we can harness two recent experimental developments to build a compact hardware emulator for the classical Heisenberg model in statistical physics. The first is the demonstration of spin-diffusion lengths in excess of microns in graphene even at room temperature. The second is the demonstration of low barrier magnets (LBMs) whose magnetization can fluctuate rapidly even at sub-nanosecond rates. Using experimentally benchmarked circuit models, we show that an array of LBMs driven by an external current source has a steady-state distribution corresponding to a classical system with an energy function of the form $E = -1/2\sum_{i,j} J_{ij} (\hat{m}_i \cdot \hat{m}_j$). This may seem surprising for a non-equilibrium system but we show that it can be justified by a Lyapunov function corresponding to a system of coupled Landau-Lifshitz-Gilbert (LLG) equations. The Lyapunov function we construct describes LBMs interacting through the spin currents they inject into the spin neutral substrate. We suggest ways to tune the coupling coefficients $J_{ij}$ so that it can be used as a hardware solver for optimization problems involving continuous variables represented by vector magnetizations, similar to the role of the Ising model in solving optimization problems with binary variables. Finally, we train a Heisenberg XOR gate based on a network of four coupled stochastic LLG equations, illustrating the concept of probabilistic computing with a programmable Heisenberg model.

Domain-specific hardware to solve computationally hard optimization problems has generated tremendous excitement. Here, we evaluate probabilistic bit (p-bit) based Ising Machines (IM) on the 3-regular 3-Exclusive OR Satisfiability (3R3X), as a representative hard optimization problem. We first introduce a multiplexed architecture that emulates all-to-all network functionality while maintaining highly parallelized chromatic Gibbs sampling. We implement this architecture in single Field-Programmable Gate Arrays (FPGA) and show that running the adaptive parallel tempering algorithm demonstrates competitive algorithmic and prefactor advantages over alternative IMs by D-Wave, Toshiba, and Fujitsu. We also implement higher-order interactions that lead to better prefactors without changing algorithmic scaling for the XORSAT problem. Even though FPGA implementations of p-bits are still not quite as fast as the best possible greedy algorithms accelerated on Graphics Processing Units (GPU), scaled magnetic versions of p-bit IMs could lead to orders of magnitude improvements over the state of the art for generic optimization., Comment: S.N, S. K, N.A.A are equally contributing first authors

Stochastic magnetic tunnel junctions (sMTJ) using low-barrier nanomagnets have shown promise as fast, energy-efficient, and scalable building blocks for probabilistic computing. Despite recent experimental and theoretical progress, sMTJs exhibiting the ideal characteristics necessary for probabilistic bits (p-bit) are still lacking. Ideally, the sMTJs should have (a) voltage bias independence preventing read disturbance (b) uniform randomness in the magnetization angle between the free layers, and (c) fast fluctuations without requiring external magnetic fields while being robust to magnetic field perturbations. Here, we propose a new design satisfying all of these requirements, using double-free-layer sMTJs with synthetic antiferromagnets (SAF). We evaluate the proposed sMTJ design with experimentally benchmarked spin-circuit models accounting for transport physics, coupled with the stochastic Landau-Lifshitz-Gilbert equation for magnetization dynamics. We find that the use of low-barrier SAF layers reduces dipolar coupling, achieving uncorrelated fluctuations at zero-magnetic field surviving up to diameters exceeding ($D\approx 100$ nm) if the nanomagnets can be made thin enough ($\approx 1$-$2$ nm). The double-free-layer structure retains bias-independence and the circular nature of the nanomagnets provides near-uniform randomness with fast fluctuations. Combining our full sMTJ model with advanced transistor models, we estimate the energy to generate a random bit as $\approx$ 3.6 fJ, with fluctuation rates of $\approx$ 3.3 GHz per p-bit. Our results will guide the experimental development of superior stochastic magnetic tunnel junctions for large-scale and energy-efficient probabilistic computation for problems relevant to machine learning and artificial intelligence.

The slowing down of Moore's Law has led to a crisis as the computing workloads of Artificial Intelligence (AI) algorithms continue skyrocketing. There is an urgent need for scalable and energy-efficient hardware catering to the unique requirements of AI algorithms and applications. In this environment, probabilistic computing with p-bits emerged as a scalable, domain-specific, and energy-efficient computing paradigm, particularly useful for probabilistic applications and algorithms. In particular, spintronic devices such as stochastic magnetic tunnel junctions (sMTJ) show great promise in designing integrated p-computers. Here, we examine how a scalable probabilistic computer with such magnetic p-bits can be useful for an emerging field combining machine learning and quantum physics.

Extending Moore's law by augmenting complementary-metal-oxide semiconductor (CMOS) transistors with emerging nanotechnologies (X) has become increasingly important. One important class of problems involve sampling-based Monte Carlo algorithms used in probabilistic machine learning, optimization, and quantum simulation. Here, we combine stochastic magnetic tunnel junction (sMTJ)-based probabilistic bits (p-bits) with Field Programmable Gate Arrays (FPGA) to create an energy-efficient CMOS + X (X = sMTJ) prototype. This setup shows how asynchronously driven CMOS circuits controlled by sMTJs can perform probabilistic inference and learning by leveraging the algorithmic update-order-invariance of Gibbs sampling. We show how the stochasticity of sMTJs can augment low-quality random number generators (RNG). Detailed transistor-level comparisons reveal that sMTJ-based p-bits can replace up to 10,000 CMOS transistors while dissipating two orders of magnitude less energy. Integrated versions of our approach can advance probabilistic computing involving deep Boltzmann machines and other energy-based learning algorithms with extremely high throughput and energy efficiency.

The commercial and industrial demand for the solution of hard combinatorial optimization problems push forward the development of efficient solvers. One of them is the Ising machine which can solve combinatorial problems mapped to Ising Hamiltonians. In particular, spintronic hardware implementations of Ising machines can be very efficient in terms of area and performance, and are relatively low-cost considering the potential to create hybrid CMOS-spintronic technology. Here, we perform a comparison of coherent and probabilistic paradigms of Ising machines on several hard Max-Cut instances, analyzing their scalability and performance at software level. We show that probabilistic Ising machines outperform coherent Ising machines in terms of the number of iterations required to achieve the problem s solution. Nevertheless, high frequency spintronic oscillators with sub-nanosecond synchronization times could be very promising as ultrafast Ising machines. In addition, considering that a coherent Ising machine acts better for Max-Cut problems because of the absence of the linear term in the Ising Hamiltonian, we introduce a procedure to encode Max-3SAT to Max-Cut. We foresee potential synergic interplays between the two paradigms., Comment: 26 pages, 6 Figures, submitted for publication in Phys. Rev. Applied (it will be presented at intermag 2023 in Japan)

The slowing down of Moore's law has driven the development of unconventional computing paradigms, such as specialized Ising machines tailored to solve combinatorial optimization problems. In this paper, we show a new application domain for probabilistic bit (p-bit) based Ising machines by training deep generative AI models with them. Using sparse, asynchronous, and massively parallel Ising machines we train deep Boltzmann networks in a hybrid probabilistic-classical computing setup. We use the full MNIST and Fashion MNIST (FMNIST) dataset without any downsampling and a reduced version of CIFAR-10 dataset in hardware-aware network topologies implemented in moderately sized Field Programmable Gate Arrays (FPGA). For MNIST, our machine using only 4,264 nodes (p-bits) and about 30,000 parameters achieves the same classification accuracy (90%) as an optimized software-based restricted Boltzmann Machine (RBM) with approximately 3.25 million parameters. Similar results follow for FMNIST and CIFAR-10. Additionally, the sparse deep Boltzmann network can generate new handwritten digits and fashion products, a task the 3.25 million parameter RBM fails at despite achieving the same accuracy. Our hybrid computer takes a measured 50 to 64 billion probabilistic flips per second, which is at least an order of magnitude faster than superficially similar Graphics and Tensor Processing Unit (GPU/TPU) based implementations. The massively parallel architecture can comfortably perform the contrastive divergence algorithm (CD-n) with up to n = 10 million sweeps per update, beyond the capabilities of existing software implementations. These results demonstrate the potential of using Ising machines for traditionally hard-to-train deep generative Boltzmann networks, with further possible improvement in nanodevice-based realizations.

The transistor celebrated its 75${}^\text{th}$ birthday in 2022. The continued scaling of the transistor defined by Moore's Law continues, albeit at a slower pace. Meanwhile, computing demands and energy consumption required by modern artificial intelligence (AI) algorithms have skyrocketed. As an alternative to scaling transistors for general-purpose computing, the integration of transistors with unconventional technologies has emerged as a promising path for domain-specific computing. In this article, we provide a full-stack review of probabilistic computing with p-bits as a representative example of the energy-efficient and domain-specific computing movement. We argue that p-bits could be used to build energy-efficient probabilistic systems, tailored for probabilistic algorithms and applications. From hardware, architecture, and algorithmic perspectives, we outline the main applications of probabilistic computers ranging from probabilistic machine learning and AI to combinatorial optimization and quantum simulation. Combining emerging nanodevices with the existing CMOS ecosystem will lead to probabilistic computers with orders of magnitude improvements in energy efficiency and probabilistic sampling, potentially unlocking previously unexplored regimes for powerful probabilistic algorithms.

In the "Beyond Moore's Law" era, with increasing edge intelligence, domain-specific computing embracing unconventional approaches will become increasingly prevalent. At the same time, adopting a variety of nanotechnologies will offer benefits in energy cost, computational speed, reduced footprint, cyber resilience, and processing power. The time is ripe for a roadmap for unconventional computing with nanotechnologies to guide future research, and this collection aims to fill that need. The authors provide a comprehensive roadmap for neuromorphic computing using electron spins, memristive devices, two-dimensional nanomaterials, nanomagnets, and various dynamical systems. They also address other paradigms such as Ising machines, Bayesian inference engines, probabilistic computing with p-bits, processing in memory, quantum memories and algorithms, computing with skyrmions and spin waves, and brain-inspired computing for incremental learning and problem-solving in severely resource-constrained environments. These approaches have advantages over traditional Boolean computing based on von Neumann architecture. As the computational requirements for artificial intelligence grow 50 times faster than Moore's Law for electronics, more unconventional approaches to computing and signal processing will appear on the horizon, and this roadmap will help identify future needs and challenges. In a very fertile field, experts in the field aim to present some of the dominant and most promising technologies for unconventional computing that will be around for some time to come. Within a holistic approach, the goal is to provide pathways for solidifying the field and guiding future impactful discoveries., Comment: 80 pages accepted in Nano Futures

Massively parallel annealing processors may offer superior performance for a wide range of sampling and optimization problems. A key component dictating the size of these processors is the neuron update circuit, ideally implemented using special stochastic nanodevices. We leverage photon statistics using single photon avalanche diodes (SPADs) and temporal filtering to generate stochastic states. This method is a powerful alternative offering unique features not currently seen in annealing processors: the ability to continuously control the computational temperature and the seamless extension to the Potts model, a $n$-state generalization of the two-state Ising model. SPADs also offer a considerable practical advantage since they are readily manufacturable in current standard CMOS processes. As a first step towards realizing a CMOS SPAD-based annealer, we have designed Ising and Potts models driven by an array of discrete SPADs and show they accurately sample from their theoretical distributions.

Quantum Monte Carlo (QMC) techniques are widely used in a variety of scientific problems and much work has been dedicated to developing optimized algorithms that can accelerate QMC on standard processors (CPU). With the advent of various special purpose devices and domain specific hardware, it has become increasingly important to establish clear benchmarks of what improvements these technologies offer compared to existing technologies. In this paper, we demonstrate 2 to 3 orders of magnitude acceleration of a standard QMC algorithm using a specially designed digital processor, and a further 2 to 3 orders of magnitude by mapping it to a clockless analog processor. Our demonstration provides a roadmap for 5 to 6 orders of magnitude acceleration for a transverse field Ising model (TFIM) and could possibly be extended to other QMC models as well. The clockless analog hardware can be viewed as the classical counterpart of the quantum annealer and provides performance within a factor of $<10$ of the latter. The convergence time for the clockless analog hardware scales with the number of qubits as $\sim N$, improving the $\sim N^2$ scaling for CPU implementations, but appears worse than that reported for quantum annealers by D-Wave.

Probabilistic computing has emerged as a viable approach to solve hard optimization problems. Devices with inherent stochasticity can greatly simplify their implementation in electronic hardware. Here, we demonstrate intrinsic stochastic resistance switching controlled via electric fields in perovskite nickelates doped with hydrogen. The ability of hydrogen ions to reside in various metastable configurations in the lattice leads to a distribution of transport gaps. With experimentally characterized p-bits, a shared-synapse p-bit architecture demonstrates highly-parallelized and energy-efficient solutions to optimization problems such as integer factorization and Boolean-satisfiability. The results introduce perovskite nickelates as scalable potential candidates for probabilistic computing and showcase the potential of light-element dopants in next-generation correlated semiconductors.

The nearing end of Moore's Law has been driving the development of domain-specific hardware tailored to solve a special set of problems. Along these lines, probabilistic computing with inherently stochastic building blocks (p-bits) have shown significant promise, particularly in the context of hard optimization and statistical sampling problems. p-bits have been proposed and demonstrated in different hardware substrates ranging from small-scale stochastic magnetic tunnel junctions (sMTJs) in asynchronous architectures to large-scale CMOS in synchronous architectures. Here, we design and implement a truly asynchronous and medium-scale p-computer (with $\approx$ 800 p-bits) that closely emulates the asynchronous dynamics of sMTJs in Field Programmable Gate Arrays (FPGAs). Using hard instances of the planted Ising glass problem on the Chimera lattice, we evaluate the performance of the asynchronous architecture against an ideal, synchronous design that performs parallelized (chromatic) exact Gibbs sampling. We find that despite the lack of any careful synchronization, the asynchronous design achieves parallelism with comparable algorithmic scaling in the ideal, carefully tuned and parallelized synchronous design. Our results highlight the promise of massively scaled p-computers with millions of free-running p-bits made out of nanoscale building blocks such as stochastic magnetic tunnel junctions., Comment: To appear in the 22nd IEEE International Conference on Nanotechnology (IEEE-NANO 2022)

We propose a new type of magnetoelectric memory device that stores magnetic easy-axis information or pseudo-magnetization, rather than a definite magnetization direction, in piezoelectric/ferromagnetic (PE/FM) heterostructures. Theoretically, we show how a PE/FM combination can lead to non-volatility in pseudo-magnetization exhibiting ferroelectric-like behavior. The pseudo-magnetization can be manipulated by extremely low voltages especially when the FM is a low-barrier nanomagnet. Using a circuit model benchmarked against experiments, we determine the switching energy, delay, switching probability and retention time of the envisioned 1T/1C memory device in terms of magnetic and circuit parameters and discuss its thermal stability in terms of a key parameter called back-voltage vm which is an electrical measure of the strain-induced magnetic field. Taking advantage of ferromagnetic resonance (FMR) measurements, we experimentally extract values for vm in CoFeB films and circular nano-magnets deposited on Pb(Mg1/3Nb2/3)0.7Ti0.3O3 (PMN-PT) which agree well with the theoretical values. Our experimental findings indeed indicate the feasibility of the proposed novel device and confirm the assumed parameters in our modeling effort.

We propose a solid-state implementation of the Larmor clock that exploits tunnel magnetoresistance to distill information on how long itinerant spins take to traverse a barrier embedded in it. Keeping in mind that the tunnelling time innately involves pristine pre-selection and post-selection, our proposal takes into account the detrimental aspects of multiple reflections by incorporating multiple contacts, multiple current measurements and suitably defined magnetoresistance signals. Our analysis provides a direct mapping between the magnetoresistance signals and the tunneling times and aligns well with the interpretation in terms of generalized quantum measurements and quantum weak values. By means of an engineered pre-selection in one of the ferromagnetic contacts, we also elucidate how one can make the measurement "weak" by minimizing the back-action, while keeping the tunneling time unchanged. We then analyze the resulting interpretations of the tunneling time and the measurement back action in the presence of phase breaking effects that are intrinsic to solid state systems. We unravel that while the time-keeping aspect of the Larmor clock is reasonably undeterred due to momentum and phase relaxation processes, it degrades significantly in the presence of spin-dephasing. We believe that the ideas presented here also open up a fructuous solid state platform to encompass emerging ideas in quantum technology such as quantum weak values and its applications, that are currently exclusive to quantum optics and cold atoms., Comment: 8 pages, 6 figures, supplementary material included, comments welcome

Inspired by the developments in quantum computing, building domain-specific classical hardware to solve computationally hard problems has received increasing attention. Here, by introducing systematic sparsification techniques, we demonstrate a massively parallel architecture: the sparse Ising Machine (sIM). Exploiting sparsity, sIM achieves ideal parallelism: its key figure of merit - flips per second - scales linearly with the number of probabilistic bits (p-bit) in the system. This makes sIM up to 6 orders of magnitude faster than a CPU implementing standard Gibbs sampling. Compared to optimized implementations in TPUs and GPUs, sIM delivers 5-18x speedup in sampling. In benchmark problems such as integer factorization, sIM can reliably factor semiprimes up to 32-bits, far larger than previous attempts from D-Wave and other probabilistic solvers. Strikingly, sIM beats competition-winning SAT solvers (by 4-700x in runtime to reach 95% accuracy) in solving 3SAT problems. Even when sampling is made inexact using faster clocks, sIM can find the correct ground state with further speedup. The problem encoding and sparsification techniques we introduce can be applied to other Ising Machines (classical and quantum) and the architecture we present can be used for scaling the demonstrated 5,000-10,000 p-bits to 1,000,000 or more through analog CMOS or nanodevices.

One of the big challenges of current electronics is the design and implementation of hardware neural networks that perform fast and energy-efficient machine learning. Spintronics is a promising catalyst for this field with the capabilities of nanosecond operation and compatibility with existing microelectronics. Considering large-scale, viable neuromorphic systems however, variability of device properties is a serious concern. In this paper, we show an autonomously operating circuit that performs hardware-aware machine learning utilizing probabilistic neurons built with stochastic magnetic tunnel junctions. We show that $in \ situ$ learning of weights and biases in a Boltzmann machine can counter device-to-device variations and learn the probability distribution of meaningful operations such as a full adder. This scalable autonomously operating learning circuit using spintronics-based neurons could be especially of interest for standalone artificial-intelligence devices capable of fast and efficient learning at the edge.

Recently there has been increasing activity to build dedicated Ising Machines to accelerate the solution of combinatorial optimization problems by expressing these problems as a ground-state search of the Ising model. A common theme of such Ising Machines is to tailor the physics of underlying hardware to the mathematics of the Ising model to improve some aspect of performance that is measured in speed to solution, energy consumption per solution or area footprint of the adopted hardware. One such approach to build an Ising spin, or a binary stochastic neuron (BSN), is a compact mixed-signal unit based on a low-barrier nanomagnet based design that uses a single magnetic tunnel junction (MTJ) and three transistors (3T-1MTJ) where the MTJ functions as a stochastic resistor (1SR). Such a compact unit can drastically reduce the area footprint of BSNs while promising massive scalability by leveraging the existing Magnetic RAM (MRAM) technology that has integrated 1T-1MTJ cells in ~Gbit densities. The 3T-1SR design however can be realized using different materials or devices that provide naturally fluctuating resistances. Extending previous work, we evaluate hardware BSNs from this general perspective by classifying necessary and sufficient conditions to design a fast and energy-efficient BSN that can be used in scaled Ising Machine implementations. We connect our device analysis to systems-level metrics by emphasizing hardware-independent figures-of-merit such as flips per second and dissipated energy per random bit that can be used to classify any Ising Machine.

Naturally random devices that exploit ambient thermal noise have recently attracted attention as hardware primitives for accelerating probabilistic computing applications. One such approach is to use a low barrier nanomagnet as the free layer of a magnetic tunnel junction (MTJ) whose magnetic fluctuations are converted to resistance fluctuations in the presence of a stable fixed layer. Here, we propose and theoretically analyze a magnetic tunnel junction with no fixed layers but two free layers that are circularly shaped disk magnets. We use an experimentally benchmarked model that accounts for finite temperature magnetization dynamics, bias-dependent charge and spin-polarized currents as well as the dipolar coupling between the free layers. We obtain analytical results for statistical averages of fluctuations that are in good agreement with the numerical model. We find that the free layers with low diameters fluctuate to randomize the resistance of the MTJ in an approximately bias-independent manner. We show how such MTJs can be used to build a binary stochastic neuron (or a p-bit) in hardware. Unlike earlier stochastic MTJs that need to operate at a specific bias point to produce random fluctuations, the proposed design can be random for a wide range of bias values, independent of spin-transfer-torque pinning. Moreover, in the absence of a carefully optimized stabled fixed layer, the symmetric double-free layer stack can be manufactured using present day Magnetoresistive Random Access Memory (MRAM) technology by minimal changes to the fabrication process. Such devices can be used as hardware accelerators in energy-efficient computing schemes that require a large throughput of tunably random bits.

The Non-Equilibrium Green Function (NEGF) method was established in the 1960's through the classic work of Schwinger, Kadanoff, Baym, Keldysh and others using many-body perturbation theory (MBPT) and the diagrammatic theory for non-equilibrium processes. Much of the literature is based on the original MBPT-based approach and this makes it inaccessible to those unfamiliar with advanced quantum statistical mechanics. We obtain the NEGF equations directly from a one-electron Schr\"odinger equation using relatively elementary arguments. These equations have been used to discuss many problems of great interest such as quantized conductance, (integer) quantum Hall effect, Anderson localization, resonant tunneling and spin transport without a systematic treatment of many-body effects. But it goes beyond purely coherent transport allowing us to include phase-breaking interactions (both momentum-relaxing and momentum-conserving as well as spin-conserving and spin-relaxing) within a self-consistent Born approximation. We believe that the scope and utility of the NEGF equations transcend the MBPT-based approach originally used to derive it. NEGF teaches us how to combine quantum dynamics with "contacts" much as Boltzmann taught us how to combine classical dynamics with "contacts", using the word contacts in a broad, figurative sense to denote all kinds of entropy-driven processes. We believe that this approach to "contact-ing" the Schr\"odinger equation should be of broad interest to anyone working on device physics or non-equilibrium statistical mechanics in general., Comment: To appear in Springer Handbook of Semiconductor Devices (2021)

The primary objective of this paper is to present an exact and general procedure for mapping any sequence of quantum gates onto a network of probabilistic p-bits which can take on one of two values 0 and 1. The first $n$ p-bits represent the input qubits, while the other p-bits represent the qubits after the application of successive gating operations. We can view this structure as a Boltzmann machine whose states each represent a Feynman path leading from an initial configuration of qubits to a final configuration. Each such path has a complex amplitude $\psi$ which can be associated with a complex energy. The real part of this energy can be used to generate samples of Feynman paths in the usual way, while the imaginary part is accounted for by treating the samples as complex entities, unlike ordinary Boltzmann machines where samples are positive. Quantum gates often have purely imaginary energy functions for which all configurations have the same probability and one cannot take advantage of sampling techniques. However, if we can use suitable transformations to introduce a real part in the energy function then powerful sampling algorithms like Gibbs sampling can be harnessed to get acceptable results with far fewer samples and perhaps even escape the exponential scaling with $nd$. This algorithmic acceleration can then be supplemented with special-purpose hardware accelerators like Ising Machines which can obtain a very large number of samples per second through a combination of massive parallelism, pipelining, and clockless mixed-signal operation made possible by codesigning circuits and architectures to match the algorithm. Our results for mapping an arbitrary quantum circuit to a Boltzmann machine with a complex energy function should help push the boundaries of the simulability of quantum circuits with probabilistic resources and compare them with NISQ-era quantum computers.

Directed acyclic graphs or Bayesian networks that are popular in many AI related sectors for probabilistic inference and causal reasoning can be mapped to probabilistic circuits built out of probabilistic bits (p-bits), analogous to binary stochastic neurons of stochastic artificial neural networks. In order to satisfy standard statistical results, individual p-bits not only need to be updated sequentially, but also in order from the parent to the child nodes, necessitating the use of sequencers in software implementations. In this article, we first use SPICE simulations to show that an autonomous hardware Bayesian network can operate correctly without any clocks or sequencers, but only if the individual p-bits are appropriately designed. We then present a simple behavioral model of the autonomous hardware illustrating the essential characteristics needed for correct sequencer-free operation. This model is also benchmarked against SPICE simulations and can be used to simulate large scale networks. Our results could be useful in the design of hardware accelerators that use energy efficient building blocks suited for low-level implementations of Bayesian networks. The autonomous massively parallel operation of our proposed stochastic hardware has biological relevance since neural dynamics in brain is also stochastic and autonomous by nature.

Novel computational paradigms may provide the blueprint to help solving the time and energy limitations that we face with our modern computers, and provide solutions to complex problems more efficiently (with reduced time, power consumption and/or less device footprint) than is currently possible with standard approaches. Spintronics offers a promising basis for the development of efficient devices and unconventional operations for at least three main reasons: (i) the low-power requirements of spin-based devices, i.e., requiring no standby power for operation and the possibility to write information with small dynamic energy dissipation, (ii) the strong nonlinearity, time nonlocality, and/or stochasticity that spintronic devices can exhibit, and (iii) their compatibility with CMOS logic manufacturing processes. At the same time, the high endurance and speed of spintronic devices means that they can be rewritten or reconfigured frequently over the lifetime of a circuit, a feature that is essential in many emerging computing concepts. In this perspective, we will discuss how spintronics may aid in the realization of efficient devices primarily based on magnetic tunnel junctions and how those devices can impact in the development of three unconventional computing paradigms, namely, reservoir computing, probabilistic computing and memcomputing that in our opinion may be used to address some limitations of modern computers, providing a realistic path to intelligent hybrid CMOS-spintronic systems., Comment: 18 pages and 4 figures

Modern machine learning is based on powerful algorithms running on digital computing platforms and there is great interest in accelerating the learning process and making it more energy efficient. In this paper we present a fully autonomous probabilistic circuit for fast and efficient learning that makes no use of digital computing. Specifically we use SPICE simulations to demonstrate a clockless autonomous circuit where the required synaptic weights are read out in the form of analog voltages. Such autonomous circuits could be particularly of interest as standalone learning devices in the context of mobile and edge computing.

Low barrier nanomagnets have attracted a lot of research interest for their use as sources of high quality true random number generation. More recently, low barrier nanomagnets with tunable output have been shown to be a natural hardware platform for unconventional computing paradigms such as probabilistic spin logic. Efficient generation and tunability of high quality random bits is critical for these novel applications. However, current spintronic random number generators are based on superparamagnetic tunnel junctions (SMTJs) with tunability obtained through spin transfer torque (STT), which unavoidably leads to challenges in designing concatenated networks using these two terminal devices. The more recent development of utilizing spin orbit torque (SOT) allows for a three terminal device design, but can only tune in-plane magnetization freely, which is not very energy efficient due to the needs of overcoming a large demagnetization field. In this work, we experimentally demonstrate for the first time, a stochastic device with perpendicular magnetic anisotropy (PMA) that is completely tunable by SOT without the aid of any external magnetic field. Our measurements lead us to hypothesize that a tilted anisotropy might be responsible for the observed tunability. We carry out stochastic Landau-Lifshitz-Gilbert (sLLG) simulations to confirm our experimental observation. Finally, we build an electrically coupled network of two such stochastic nanomagnet based devices and demonstrate that finite correlation or anti-correlation can be established between their output fluctuations by a weak interconnection, despite having a large difference in their natural fluctuation time scale. Simulations based on a newly developed dynamical model for autonomous circuits composed of low barrier nanomagnets show close agreement with the experimental results.

In this paper we present a concrete design for a probabilistic (p-) computer based on a network of p-bits, robust classical entities fluctuating between -1 and +1, with probabilities that are controlled through an input constructed from the outputs of other p-bits. The architecture of this probabilistic computer is similar to a stochastic neural network with the p-bit playing the role of a binary stochastic neuron, but with one key difference: there is no sequencer used to enforce an ordering of p-bit updates, as is typically required. Instead, we explore \textit{sequencerless} designs where all p-bits are allowed to flip autonomously and demonstrate that such designs can allow ultrafast operation unconstrained by available clock speeds without compromising the solution's fidelity. Based on experimental results from a hardware benchmark of the autonomous design and benchmarked device models, we project that a nanomagnetic implementation can scale to achieve petaflips per second with millions of neurons. A key contribution of this paper is the focus on a hardware metric $-$ flips per second $-$ as a problem and substrate-independent figure-of-merit for an emerging class of hardware annealers known as Ising Machines. Much like the shrinking feature sizes of transistors that have continually driven Moore's Law, we believe that flips per second can be continually improved in later technology generations of a wide class of probabilistic, domain specific hardware., Comment: 13 pages, 8 figures, 1 table

Binary stochastic neurons (BSN's) form an integral part of many machine learning algorithms, motivating the development of hardware accelerators for this complex function. It has been recognized that hardware BSN's can be implemented using low barrier magnets (LBM's) by minimally modifying present-day magnetoresistive random access memory (MRAM) devices. A crucial parameter that determines the response of these LBM based BSN designs is the \emph{correlation time} of magnetization, $\tau_c$. In this letter, we show that for magnets with low energy barriers ($\Delta \approx k_BT$ and below), circular disk magnets with in-plane magnetic anisotropy (IMA) lead to $\tau_c$ values that are two orders of magnitude smaller compared to $\tau_c$ for magnets having perpendicular magnetic anisotropy (PMA) and provide analytical descriptions. We show that this striking difference in $\tau_c$ is due to a precession-like fluctuation mechanism that is enabled by the large demagnetization field in IMA magnets. We provide a detailed energy-delay performance evaluation of previously proposed BSN designs based on Spin-Orbit-Torque (SOT) MRAM and Spin-Transfer-Torque (STT) MRAM employing low barrier circular IMA magnets by SPICE simulations. The designs exhibit sub-ns response times leading to energy requirements of $\sim$a few fJ to evaluate the BSN function, orders of magnitude lower than digital CMOS implementations with a much larger footprint. While modern MRAM technology is based on PMA magnets, results in this paper suggest that low barrier circular IMA magnets may be more suitable for this application.

Fast magnetic fluctuations due to thermal torques have useful technological functionality ranging from cryptography to probabilistic computing. The characteristic time of fluctuations in typical uniaxial anisotropy magnets studied so far is bounded from below by the well-known energy relaxation mechanism. This time scales as $\alpha^{-1}$, where $\alpha$ parameterizes the strength of dissipative processes. Here, we theoretically analyze the fluctuating dynamics in easy-plane and antiferromagnetically coupled nanomagnets. We find in such magnets, the dynamics are strongly influenced by fluctuating intrinsic fields, which give rise to an additional dephasing-type mechanism for washing out correlations. In particular, we establish two time scales for characterizing fluctuations (i) the average time for a nanomagnet to reverse|which for the experimentally relevant regime of low damping is governed primarily by dephasing and becomes independent of $\alpha$, (ii) the time scale for memory loss of a single nanomagnet|which scales as $\alpha^{-1/3}$ and is governed by a combination of energy dissipation and dephasing mechanism. For typical experimentally accessible values of intrinsic fields, the resultant thermal-fluctuation rate is increased by multiple orders of magnitude when compared with the bound set solely by the energy relaxation mechanism in uniaxial magnets. This could lead to higher operating speeds of emerging devices exploiting magnetic fluctuations.

Taking advantage of the Magnetoelectric (ME) and its inverse effect, this article demonstrates strain-mediated magnetoelectric write and read operations simultaneously in Co60Fe20B20/ Pb(Mg1/3Nb2/3)0.7Ti0.3O3 heterostructures without using any symmetry breaking magnetic field at room temperature. By applying an external DC-voltage across a (011)-cut PMN-PT substrate, the ferroelectric polarization is re-oriented, which results in an anisotropic in-plane strain that transfers to the CoFeB thin film and changes its magnetic anisotropy Hk. The change in Hk in-turn results in a 90o rotation of the magnetic easy axis for sufficiently high voltages. Simultaneously, the inverse effect is employed to read changes of the magnetic properties. Because the Piezoelectric (PE)/FerroMagnetic (FM) system is fully coupled, the change of magnetization in FM induces an elastic stress in the PE layer, which generates a piezoelectric potential in the system that can be used to readout the magnetic state of the FM layer. Our experimental results are in excellent qualitative agreement with a recently proposed, experimentally benchmarked equivalent circuit model that considers how magnetic properties are electrically controlled in such ME/PE heterostructure and how a back-voltage is generated due to changing magnetic properties in a self-consistent model.

We present a low barrier magnet based compact hardware unit for analog stochastic neurons and demonstrate its use as a building-block for neuromorphic hardware. By coupling circular magnetic tunnel junctions (MTJs) with a CMOS based analog buffer, we show that these units can act as leaky-integrate-and fire (LIF) neurons, a model of biological neural networks particularly suited for temporal inferencing and pattern recognition. We demonstrate examples of temporal sequence learning, processing, and prediction tasks in real time, as a proof of concept demonstration of scalable and adaptive signal-processors. Efficient non von-Neumann hardware implementation of such processors can open up a pathway for integration of hardware based cognition in a wide variety of emerging systems such as IoT, industrial controls, bio- and photo-sensors, and Unmanned Autonomous Vehicles., Comment: 4 pages, 4 figures, under review

The coupling of spin-orbit materials to high energy barrier ($\sim$40-60 $k_BT$) nano-magnets has attracted growing interest for exciting new physics and various spintronic applications. We predict that a coupling between the spin-momentum locking (SML) observed in spin-orbit materials and low-energy barrier magnets (LBM) should exhibit a unique multi-terminal rectification for arbitrarily small amplitude channel currents. The basic idea is to measure the charge current induced spin accumulation in the SML channel in the form of a magnetization dependent voltage using an LBM, either with an in-plane or perpendicular anisotropy (IMA or PMA). The LBM feels an instantaneous spin-orbit torque due to the accumulated spins in the channel which causes the average magnetization to follow the current, leading to the non-linear rectification. We discuss the frequency band of this multi-terminal rectification which can be understood in terms of the angular momentum conservation in the LBM. For a fixed spin-current from the SML channel, the frequency band is same for LBMs with IMA and PMA, as long as they have the same total magnetic moment in a given volume. The proposed all-metallic structure could find application as highly sensitive passive rf detectors and as energy harvesters from weak ambient sources where standard technologies may not operate.

Magnetoresistive random access memory (MRAM) technologies with thermally unstable nanomagnets are leveraged to develop an intrinsic stochastic neuron as a building block for restricted Boltzmann machines (RBMs) to form deep belief networks (DBNs). The embedded MRAM-based neuron is modeled using precise physics equations. The simulation results exhibit the desired sigmoidal relation between the input voltages and probability of the output state. A probabilistic inference network simulator (PIN-Sim) is developed to realize a circuit-level model of an RBM utilizing resistive crossbar arrays along with differential amplifiers to implement the positive and negative weight values. The PIN-Sim is composed of five main blocks to train a DBN, evaluate its accuracy, and measure its power consumption. The MNIST dataset is leveraged to investigate the energy and accuracy tradeoffs of seven distinct network topologies in SPICE using the 14nm HP-FinFET technology library with the nominal voltage of 0.8V, in which an MRAM-based neuron is used as the activation function. The software and hardware level simulations indicate that a $784\times200\times10$ topology can achieve less than 5% error rates with $\sim400 pJ$ energy consumption. The error rates can be reduced to 2.5% by using a $784\times500\times500\times500\times10$ DBN at the cost of $\sim10\times$ higher energy consumption and significant area overhead. Finally, the effects of specific hardware-level parameters on power dissipation and accuracy tradeoffs are identified via the developed PIN-Sim framework.