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This paper presents a brief review of experimental and theoretical studies on a three-dimensional heterostructure consisting of vertical carbon nanotubes (CNTs) connected perpendicularly to a graphene layer. This structure can serve as a potential building block for an all-carbon network in energy storage devices and on-chip interconnects. The review highlights reported works on the fabrication and characterization of such a heterostructure, with focus on the effect of the CNT-graphene interface on electrical conduction. While a direct comparison between experiment and theory is not possible at this time, a brief survey of theoretical efforts based on atomic cluster models nonetheless reveals important knowledge about the electronic transport properties of this all-carbon heterostructure.

Vertically aligned carbon nanotube (VACNT) arrays have been explored as an absorber of thermal-type photodetectors. A long and dense VACNT array absorbs a wide spectral range of incident light with high absorption rate, but has a high thermal mass that results in a low response speed. To achieve a small thermal mass, a shorter and less dense VACNT array is needed. In addition, the high temperature needed to grow the VACNTs is detrimental to the functional sensing materials of the photodetector. The height, density, and growth temperature of VACNTs need to be optimized to achieve a working absorber that has high absorption rate and a high response speed. In this work, a low-temperature plasma enhanced chemical vapor deposition process is used to prepare various VACNT arrays with different heights and densities by controlling the CNT growth parameters. The absorption coefficients of the resulting samples are measured with Fourier transform infrared spectroscopy. An effective medium theory (EMT) is adopted to establish a working model of the VACNTs. Using experimentally extracted CNT density and height as fitting parameters, the EMT model is fitted to obtain theoretical absorption coefficients, which are found to be comparable to the experimentally measured absorption coefficients. Our experimental and theoretical investigations pave the way for future studies to integrate CNTs with infrared photodetectors.

Continuous downward scaling in silicon integrated circuit technology into the sub-20 nm regime has created critical challenges in chip manufacturing, among them, reliability and performance of on-chip interconnects. Current interconnect materials, Cu and W, face increased reliability challenges in the nanoscale as a result of electromigration failures at high current densities. Materials such as nanocarbons, metal silicides, cobalt, ruthenium, and metallic nanowires are being considered as potential replacements for Cu and W. In particular, due to its superior electrical and mechanical properties as well as much higher current-carrying capacities, carbon nanotube (CNT) has been demonstrated to be a serious contender in on-chip interconnect vias. However, the main challenge to functionalizing CNT vias is the metal-CNT contact resistance. To mitigate such challenge, a seamless three-dimensional all-carbon interconnect structure is conceived and fabricated by growing CNTs directly on one or few layers of graphene (MLG). This 3D structure can potentially yield low resistance due to the strong C-C sp2 bonding in CNT and graphene and across the CNT-graphene interface. While such growth has been demonstrated, the CNT/graphene interfacial nanostructure and how it impacts the electrical properties of the 3D structure are far from being understood.

Continuous downward scaling in silicon integrated circuit technology into the sub-20 nm regime has created critical challenges in chip manufacturing, among them, reliability and performance of on-chip interconnects. Current interconnect materials, Cu and W, face increased reliability challenges in the nanoscale as a result of electromigration failures at high current densities. Materials such as nanocarbons, metal silicides, cobalt, ruthenium, and metallic nanowires are being considered as potential replacements for Cu and W. In particular, due to its superior electrical and mechanical properties as well as much higher current-carrying capacities, carbon nanotube (CNT) has been demonstrated to be a serious contender in on-chip interconnect vias. However, the main challenge to functionalizing CNT vias is the metal-CNT contact resistance. To mitigate such challenge, a seamless three-dimensional all-carbon interconnect structure is conceived and fabricated by growing CNTs directly on one or few layers of graphene (MLG). This 3D structure can potentially yield low resistance due to the strong C-C sp2 bonding in CNT and graphene and across the CNTgraphene interface. While such growth has been demonstrated, the CNT/graphene interfacial nanostructure and how it impacts the electrical properties of the 3D structure are far from being understood.

A comprehensive review of challenges and potential solutions associated with the impact of downscaling of integrated circuit (IC) feature sizes on on-chip interconnect materials is presented. The adoption of Moore's Law has led to developments and manufacturing of transistors with nanoscale dimensions, faster switching speeds, lower power consumption, and lower costs in recent generations of IC technology nodes. However, shrinking dimensions of wires connecting transistors have resulted in degradations in both performance and reliability, which in turn limit chip speed and lifetime. Therefore, to sustain the continuous downward scaling, alternative interconnect conductor materials to replace copper (Cu) and tungsten (W) must be explored to meet and overcome these challenges.

In this paper, a high cost-performance surface-enhanced Raman scattering (SERS) flexible substrate is demonstrated, which endowed with excellent optical transparency, high SERS activity and large scale. This SERS flexible substrate of Ag/Cu/Polyethylene Terephthalate (PET) was prepared by replacing Cu atoms with Ag atoms in situ on Cu nano-film. The Ag/Cu/PET flexible substrate shows high sensitivity in SERS detection and the minimum detected concentration of R6G can reach 10−10 M. In addition, the residual methylene blue (MB) on a fish surface was selected as the analyte, the results no doubt shows the potential of SERS technology application in food detection.

The continuous downward scaling in integrated circuit (IC) technologies has led to rapid shrinking of transistor and interconnect feature sizes. While scaling benefits transistors by increasing the switching speed and reducing the power consumption, it has an adverse impact on interconnects by degrading its electrical performance and reliability. Scaling causes reduction in interconnect linewidth, which leads to surge in resistance due to increased contributions from grain boundary and surface scattering of electrons in the metal lines. Further, current density inside interconnects is also enhanced by the reduced linewidth and is approaching or exceeding the current-carrying capacity of the existing interconnect metals, copper (Cu) and tungsten (W). The resulting failure due to electromigration presents a critical challenge for end-of-roadmap IC technology nodes. Therefore, alternative materials such as nanocarbons and silicides are being investigated as potential replacements for Cu and W as they have superior electrical and mechanical properties in the nanoscale. In this review, the electrical properties of nanocarbons, in particular carbon nanotubes (CNTs), are examined and their performance and reliability in the sub-100 nm regime are assessed. Further, the measured properties are used to project 30 nm CNT via properties, which are compared with those of Cu and W.

In this work, we present a novel optical fiber SERS (OF-SERS) sensor based on a sandwich structure of GO/AgNPs/rGO. Rhodamine 6G (R6G) was selected as the probe molecule to compare the SERS ability of different films composed of the bare optical fiber, GO, AgNPs, rGO/AgNPs, GO/AgNPs and GO/AgNPs/rGO. Raman spectra, scanning electron microscopy (SEM), atomic force microscopy (AFM), energy dispersive spectroscopy (EDS) and X-ray photoelectron spectroscopy (XPS) were performed to characterize the sandwich structure hybrid films. Besides, the stability of GO/AgNPs and GO/AgNPs/rGO was compared on the optical fiber end face. The OF-SERS sensor based GO/AgNPs/rGO hybrid films had stable SERS performance even when exposed to ambient conditions for a prolonged time of 30 days. This work may provide a new strategy for an efficient stable OF-SERS sensor due to its simplicity, low-cost and long-term stability.

We present a review of existing published works on carbon nanostructures such as graphene, carbon nanotubes, and carbon nanofibers, including their use as MOSFET channel and/or interconnect materials. The characteristics of material contacts with carbon-based nanostructures are examined for potential applications in flexible wearable electronics. Combining results of electrical measurements and interface characterization provides the necessary knowledge for continuous improvements of the nanostructure fabrication process and contact properties.

Carbon nanotube and graphene are potential candidate materials for nanoelectronics applications due to their tolerance to electromigration under high current densities and excellent electrical, thermal, and mechanical properties. In this paper, we address the key challenges for integrating carbon-based nanostructures in flexible electronics. Toward this end, we review both the applications of nanocarbon materials as passive components and active components, and address the common problems in nanocarbon electronics. We further explore the potential of an all-carbon nanostructure for various electronic device applications.

Heterostructures of carbon nanotube on graphene, CNT-graphene, with two graphene layers connected by a CNT normal to the graphene planes, are investigated using first-principle calculations, leading to computed density of states (DOS) and electron transmission spectra. Based on these results, the structure consisting of graphene and a (4,4) CNT is determined to be metallic while that of graphene and (8,0) CNT semiconducting. Multiple peaks are observed in the transmission spectrum of both heterostructures, which depend on the width of graphene. Further, it is found that the heterostructures are three-dimensional thermal conductors, although the resistance is higher than that of pure graphene or CNT. These results lay the foundation for further studies of CNT-graphene as a potential all-carbon interconnect building block.

Carbon nanotubes (CNTs) and carbon nanofibers (CNFs) are potential materials for high-performance electronic devices and circuits due to their light weight and excellent electrical properties such as high current capacity and tolerance to electromigration. In addition, at high frequencies, these materials exhibit transport behavior which holds special promise for applications as on-chip interconnects. Contact resistance at CNF-metal interface is a major factor in limiting the electrical performance of CNF interconnects at all frequencies. In this paper, it is demonstrated that the contact resistance can be minimized and the high-frequency characteristics much enhanced by depositing tungsten on CNF-metal electrode contacts.

We report resistance results from carbon nanotube (CNT) vias of widths from 150 to 60 nm for potential application in integrated circuits technology. Selective CNT growth inside the vias with an areal density of $2\times 10^{11}$ / $\mathrm{cm}^{2}$ is achieved with a statistical average resistance of 1.7 $\text{k}\Omega $ with standard deviation between $420~\Omega $ and 7.1 $\text{k}\Omega $ , and lowest resistance of 150 $\Omega $ for 60 nm vias, the lowest reported value for sub-100 nm-CNT vias. Statistical analysis yields a best-case projected value of $295~\Omega $ for a 30 nm via, within one order of magnitude of its copper and tungsten counterparts.

Performance of surface acoustic wave (SAW) resonators based on (002)AlN/Pt/diamond/silicon layered structure is demonstrated. Three resonators with different wavelengths and center frequencies in the GHz range are designed and constructed without using submicron device fabrication processes, due to the high acoustic velocity of the layered structure. The enhanced performance of the SAW resonator by introducing a thin metal layer between the diamond and AlN layers is demonstrated theoretically and experimentally. Dependence of the SAW propagation characteristics on the normalized AlN film thickness is determined and the experimental results are in good agreement with theoretical predictions. In particular, for the 1st wave mode, a very high SAW velocity of 13,656 m/s and an electromechanical coupling coefficient of 0.37% are obtained. These results demonstrate that the (002)AlN/Pt/diamond/silicon layered structure is very promising for high-frequency SAW device applications.

Carbon nanotubes (CNTs) and graphene are potential candidates for future interconnect materials. CNTs are promising on-chip via interconnect materials due to their readily formed vertical structures, their current-carrying capacity, which is much larger than existing on-chip interconnect materials such as copper and tungsten, and their demonstrated ability to grow in patterned vias with sub-50 nm widths; meanwhile, graphene is suitable for horizontal interconnects. However, they both present the challenge of having high-resistance contacts with other conductors. An all-carbon structure is proposed in this paper, which can be formed using the same chemical vapor deposition method for both CNTs and graphene. Vertically aligned CNTs are grown directly on graphene with an Fe or Ni catalyst. The structural characteristics of the graphene and the grown CNTs are analyzed using Raman spectroscopy and electron microscopy techniques. The CNT-graphene interface is studied in detail using transmission electron microscopic analysis of the CNT-graphene heterostructure, which suggests C−C bonding between the two materials. Electrical measurement results confirm the existence of both a lateral conduction path within graphene and a vertical conduction path in the CNT-graphene heterostructure, giving further support to the C−C bonding at the CNT-graphene interface and resulting in potential applications for all-carbon interconnects.

Carbon nanotubes (CNTs) are promising materials for on-chip interconnect contacts and vias. We report results on 40 nm top-contact metallized CNT vias consisting of the first experimentally extracted contact resistance for this linewidth and current-carrying capacity two orders of magnitude higher than their Cu and W counterparts, well above the ITRS roadmap specifications. To obtain via resistance comparable to those of Cu and W, contact engineering remains a challenge but can be facilitated with the reported contact resistance extraction scheme.

Aluminum nitride (AlN) piezoelectric thin films with c-axis crystal orientation on polymer substrates can potentially be used for development of flexible electronics and lab-on-chip systems. In this study, we investigated the effects of deposition parameters on the crystal structure of AlN thin films on polymer substrates deposited by reactive direct-current magnetron sputtering. The results show that low sputtering pressure as well as optimized N2/Ar flow ratio and sputtering power is beneficial for AlN (002) orientation and can produce a highly (002) oriented columnar structure on polymer substrates. High sputtering power and low N2/Ar flow ratio increase the deposition rate. In addition, the thickness of Al underlayer also has a strong influence on the film crystallography. The optimal deposition parameters in our experiments are: deposition pressure 0.38 Pa, N2/Ar flow ratio 2:3, sputtering power 414 W, and thickness of Al underlayer less than 100 nm.

Continuous downward scaling in silicon integrated circuit technology into the sub-20 nm regime has created critical challenges in chip manufacturing, among them, reliability and performance of on-chip interconnects. Current interconnect materials, Cu and W, face increased reliability challenges in the nanoscale as a result of electromigration failures at high current densities. Materials such as nanocarbons, metal silicides, and metallic nanowires are being considered as potential replacements for Cu and W. In particular, due to its superior electrical and mechanical properties as well as much higher current-carrying capacities, carbon nanotube (CNT) is a serious contender to replace Cu and W in on-chip interconnect via. However, the main challenge to functionalizing CNT vias is the metal-CNT contact resistance. To mitigate such challenge, a seamless three-dimensional all-carbon interconnect structure has been fabricated by growing CNTs directly on one or few layers of graphene (MLG). This 3D structure can potentially yield low resistance due to the strong C-C sp2 bonding in CNT and graphene and across the CNT-graphene interface. While such growth has been demonstrated, the CNT/graphene interfacial nanostructure and how it impacts the electrical properties of the 3D structure are far from being understood. Our test structure consists of MLG grown by annealing a Ni thin film in H2/CH4 ambient inside a low-pressure PECVD chamber, before being transferred onto an oxide-covered silicon substrate. Vertically aligned CNTs are then grown on the transferred MLG in a PECVD system using a similar recipe as in our previous work on CNT vias, resulting in a 3D all-carbon interconnect structure. Scanning and transmission electron microscopy images reveal CNT alignment and interfacial nanostructure comparable to the CNT-Cr interface in CNT via. The measured resistance of the 3D structure is compared with those of sub-100 nm linewidth CNT vias. Our results demonstrate the feasibility of fabricating a 3D CNT/graphene device, which can serve as the building block for all-carbon interconnects. Enhanced understanding of the relationship between interfacial nanostructure and device resistance can lead to eventual functionalization of contacts between CNT vias and a graphene-based planar interconnect network in the most advanced technology nodes.

A major challenge for carbon nanotube (CNT) to become a viable replacement of copper and tungsten in the next-generation on-chip via interconnects is the high contact resistance between CNT and metal electrodes. A first step in meeting this challenge is an accurate characterization of via contact resistance. In this paper, the scanning electron microscope (SEM) image contrast at low landing energy is employed to estimate the conductive CNT area inside vias. The total conductive CNT area inside each via is deduced using SEM image with 0.1 keV landing energy and a specified threshold brightness, yielding via resistance versus CNT area behavior, which correlates well with electrical nanoprobing measurements of via resistance. Monte Carlo simulation of secondary electron generation lends further support for our analysis and suggests that the residue covering the CNT does not affect the conduction across the contact for residue thickness below 1 nm. This imaging and analysis technique can add much value to CNT...

An empirical model is developed that takes into account heat transport through the entire carbon nanofiber interconnect test structure and breakdown location. This electrothermal transport model elucidates observed current capacity behavior, and predicts variations in contact location with the support material. The resulting heat dissipation and current capacity are completely consistent with measurement data.

The physical origin of kinetic inductance is examined for 1-D nanostructures, where the Fermi liquid theory prevails. In order to have appreciable kinetic inductance, ballistic transport must exist, with no inelastic scattering inside the nanowires. Kinetic inductance is assigned to the nanowire itself and independent of its surroundings, whereas magnetic inductance is assigned to the nanowire and substrate. Kinetic and magnetic inductances are in series in an equivalent circuit representation. If there are m transmission modes and n multiwalls in the nanostructure, kinetic inductance decreases by a factor of 1/(mn). The relation of the predicted results to preliminary experimental findings is discussed.

We show that the simplest possible circuit model of high-frequency electrical conduction in carbon nanofibers from 0.1 to 50 GHz is a frequency-independent resistor in parallel with a frequency-independent capacitor. The resistance is experimentally determined and represents the total dc resistance of the nanofiber and its contacts with the electrodes. The capacitance is obtained as a free parameter and has not been previously observed. The experimental method utilizes a ground-signal-ground test structure whose two-port scattering parameters (S-parameters) can be described to within plusmn0.5 dB and plusmn2deg using a simple lumped-element circuit model. The nanostructure is placed in the signal path of the test structure, and its equivalent circuit is deduced by determining what additional elements must be added to the test structure circuit model to reproduce the resulting changes in the S-parameters. This methodology is applicable to nanowires and nanotubes.

The rigorous application of multiple-scattering theory to contiguous nonoverlapping truncated atomic spheres leads to a molecular-orbital secular determinant which is identical to that solved in the overlapping-sphere SCF-X..cap alpha.. scattered-wave method, except for the subtraction of on-diagonal and off-diagonal terms associated with multiple scattering in the overlap regions. The possible importance and approximate evaluation of these terms as corrections to the overlapping-sphere method are discussed.

A relativistic scattered-wave formalism based on the one-electron Dirac equation is used to calculate the electronic structure of PbSe clusters both with and without point defects. The specific defects considered are vacancies, and substitutional and interestitial hydrogen atoms. The results show that the experimentally observed change in the electrical conductivity of PbSe upon exposure to atomic hydrogen is only compatible with hydrogen occupying the Pb vacancy.

We present temperature-dependent electrical characteristics of vertically aligned carbon nanofiber (CNF) arrays for on-chip interconnect applications. The study consists of three parts. First, the electron transport mechanisms in these structures are investigated using I-V measurements over a broad temperature range (4.4 K to 350 K). The measured resistivity in CNF arrays is modeled based on known graphite two-dimensional hopping electron conduction mechanism. The model is used because of the disordered graphite structure observed during high-resolution scanning transmission electron microscopy (STEM) of the CNF and CNF-metal interface. Second, electrical reliability measurements are performed at different temperatures to demonstrate the robust nature of CNFs for interconnect applications. Finally, some guidance in catalyst material selection is presented to improve the nanostructure of CNFs, making the morphology similar to multiwall nanotubes.

A dc plasma enhanced chemical vapor deposition process is used to obtain vertically aligned carbon nanofibers (CNFs) from palladium catalysts using an ammonia–acetylene process gas mixture. Transmission electron microscopy is used to elucidate the microstructure of the as-grown fibers revealing different growth anomalies such as a new secondary growth phenomenon which we term hybrid tip growth. Also included in our analysis are conventional tip growth derived structures. In a few instances, the conventional tip growth derived structures possess elongated catalyst particles that impart small cone angles to the carbon nanofiber microstructure. Detailed microchemical analysis reveals that hybrid tip grown CNFs using thick Pd films are partially filled with Pd. Analysis of these growth phenomenon and implications for potential use as on-chip interconnects are discussed.

Electron-beam-induced deposited-tungsten (EBID-W) technique is used to fabricate contacts for carbon nanofiber (CNF) horizontal interconnect and carbon nanotube (CNT) vertical vias to improve the contact resistances at the nanocarbon-metal electrodes.

We propose a novel technique for characterizing interfacial structures in vertically aligned carbon nanofibers (CNFs) utilizing scanning transmission electron microscopy (STEM). In this technique, vertically aligned CNFs are selectively grown using plasma-enhanced chemical vapor deposition (PECVD), on a substrate comprising a narrow strip (width ∼100 nm) formed by focused ion beam. Using STEM, we obtain images of nanostructures of CNFs having diameters as small as 10 nm, while focusing on the interfacial region near the nanofiber base. Stacked graphite sheets parallel to the substrate are observed near the base of these CNFs.

Electrical properties of plasma-enhanced chemical vapor deposited carbon nanofibers (CNFs) are characterized with measurements over a broad temperature range (4-300 K). Temperature-dependent measurements of CNF via resistivity reveal a behavior resembling the mixture of graphite a-axis and c-axis transport mechanisms. For the first time, temperature-dependent characteristics of CNFs are measured and modeled based on previously developed models for electron conduction in graphite. Reliability measurements are performed to demonstrate the robust electrical and thermal properties of CNF vias for next-generation on-chip-interconnect designs.

An efficient extraction and modeling methodology for self and mutual inductances within multiconductors for on-chip interconnects is investigated. The method is based on physical layout considerations and current distribution on multiple return paths, leading to loop inductance and resistance. It provides a lumped circuit model suitable for timing analysis in any circuit simulator, which can represent frequency-dependent characteristics. This novel modeling methodology accurately provides the mutual inductance and resistance as well as self terms within a wide frequency range without using any fitting algorithm. Measurement results for single and coupled wires within a multiconductor system, fabricated using 0.13 and 0.18 /spl mu/m CMOS technologies, confirm the validity of the proposed method. Our methodology can be applicable to high-speed global interconnects for post-layout as well as prelayout extraction and modeling.

We report high-frequency surface acoustic wave (SAW) devices with excellent temperature stability using a layered structure consisting of single-crystal LiNbO3 thin film on SiO2/LiNbO3 substrate. SAW devices with a wavelength of 2 μm have been fabricated and several wave modes ranging from ~ 1.5 to 2.1 GHz have been obtained. With the SiO2 interlayer providing the temperature compensation and the top single-crystal Z-cut LiNbO3 piezoelectric thin film for acoustic wave excitation, the fabricated SAW devices exhibit excellent temperature coefficients of frequency. Theoretical calculations are presented to elucidate temperature compensation of the proposed layered structure.

Nanoengineered materials have emerged as efficient thermal interface materials in a variety of thermal management applications. For example, integrated circuits (IC) are subject to tight thermal budgets to maintain acceptable reliability standards. This letter presents thermal contact resistance measurement results and analyses for copper gap-filled carbon nanofiber−copper composite arrays. Experimental results demonstrate the efficient interfacial thermal conduction of these structures. Using copper as a gap-fill material for improving lateral heat spreading and mechanical stability is discussed.

In this paper, we examine mechanisms of electron transport across the metal-carbon nanotube (CNT) interface for two different types of multiwall carbon nanotube (MWNT) architectures, horizontal or side-contacted MWNTs and vertical or end-contacted MWNTs. Horizontally aligned nanotube growth and electrical characteristics are examined with respect to their potential applications in silicon-based technologies. Recent advances in the synthesis techniques of vertical MWNTs have also enhanced the possibility for a manufacturable solution incorporating this novel material as on-chip interconnects or vias as copper interconnect feature sizes are scaled into the sub-100-nm regime. A vertical MWNT architecture is presented that may be suitable for integration into silicon-based technologies. The growth method for this architecture and its effect on electrical characteristics are examined. Through simulations, dc measurements, and comparison of our results with previous studies, we explain why high contact resistance is observed in metal-CNT-metal systems.

In this paper, we propose a compact on-chip interconnect model for full-chip simulation. The model consists of two components, a quasi-three-dimensional (3-D) capacitance model and an effective loop inductance model. In the capacitance model, we propose a novel concept of effective width (W/sub eff/) for a 3-D wire, which is derived from an analytical two-dimensional (2-D) model combined with a new analytical "wall-to-wall" model. The effective width provides a physics-based approach to decompose any 3-D structure into a series of 2-D segments, resulting in an efficient and accurate capacitance extraction. In the inductance model, we use an effective loop inductance approach for an analytic and hierarchical model construction. In particular, we show empirically that high-frequency signals (above multi-GHz) propagating through random signal lines can be approximated by a quasi-TEM mode relationship, leading to a simple way to extract the high-frequency inductance from the capacitance of the wire. Finally, the capacitance and inductance models are combined into a unified frequency-dependent RLC model, describing successfully the wide-band characteristics of on-chip interconnects up to 100 GHz. Non-orthogonal wire architecture is also investigated and included in the proposed model.

Channel electron and hole mobilities in MOSFETs have been extracted in terms of the effective vertical field for several substrate biases. After ascertaining that the 2-D drift–diffusion numerical device simulator is reproducing the substrate charge variation in the MOSFET with respect to the gate voltage, obtained from C–V data, the mobility versus effective field behavior is extracted by comparing the simulated and measured Id–Vgs characteristics. A simple model has been constructed to fit the extracted mobility data in weak and strong inversion, for inversion-layer electrons and holes in n-MOSFET and p-MOSFET, respectively.