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Today’s wireless devices, like our smartphones, are able to handle multiple standards and bands for different applications, such as Bluetooth, Wi-Fi and data-voice communications. However, the cost of a modern transceiver is becoming mainly dominated by the large number of off-chip passive components, like Duplexers and SAW filters, needed to distinguish the desired signal among many interferences. Addressing the challenges that arise from the lack of RF filtering, a SAW-less architecture represents an interesting solution to reduce the platform complexity. This thesis proposes a feasible solution based on a SAW-less RF front-end able to meet the standard requirements and a digital system tailored to the RF path. The digital architecture, which represents the main topic of this thesis, is described in detail and experimentally tested to validate the proposed solutions.

El presente trabajo, ilustra el surgimiento de una nueva lex mercatoria a nivel global,semejante al derecho de los comerciantes en la Edad Media, diseñada para regular las relaciones empresariales transnacionales,superando la discontinuidad jurídica provocada por las codificaciones de los estados nacionales. This work illustrates the emergence of a new lex mercatoria at global level, similar to the merchant law of the Middle Ages, designed to regulate the transnational entrepreneurial relationships, overcoming the legal discontinuity caused by the codifications of the national estates.

The generation of complex signal sources is important for test and validation of electronic systems. With reference to noise sources, commercial systems usually provide white noise sources, while the scientific literature only recently proposed circuits that generate programmable colored noise. This paper proposes a filtering circuit and an algorithm to design the same that produces an arbitrary colored electrical noise. The proposed system improves the performances of the previously proposed circuits in terms of spectral characteristics of the output, in terms of logic resource occupation and power dissipation, while providing no penalty on the working frequency.

NAND-based digitally controlled delay-lines (DCDLs) are employed in several applications owing to their excellent linearity, good resolution and easy standard cell design. A glitch-free DCDL behavior is often a strict requirement [e.g. spread-spectrum clock generators (SSCG) and digitally controlled oscillators]. Existing glitch-free NAND-based DCDL topologies either require two flip-flops for each DCDL delay-element (DE) or present a very long settling time which limits the maximum working frequency. This paper proposes a novel glitch-free NAND-based DCDL that joins the advantages of previously proposed topologies: uses only a single flip-flop for each DE (reducing area and power) and has relaxed timing requirements (allowing easy integration in applications like SSCG). In the paper, the glitch-free operation of the proposed circuit is firstly demonstrated theoretically and then verified experimentally, with the help of an SSCG built using proposed DCDL and implemented in 28 nm CMOS. Simulation results show that proposed DCDL results in a more that 30 % reduction of the power dissipation and a >20 % reduction in area occupation with respect to double flip-flop DCDL, without any timing constraints penalty.

The paper proposes a SISO register circuit, functionally equivalent to a Shift Register, that is the optimal design choice when the input data have a reduced transition probability. The proposed circuit obtains improved performances by only storing the transitions of the input data, thus saving logic and power.

This paper presents the analysis and hardware implementation of a low-power control system for a frequency-division duplexing 3G receiver with a tunable on-chip duplexer based on a hybrid-transformer. The maximum transmit-receive isolation exceeds 60dB and is limited by the precision of the on-chip balancing impedance. An optimization algorithm finds the optimal duplexer tuning condition in less than 100μs and a simple tracking algorithm operating in background preserves this condition over time. The algorithms are implemented in a FPGA and require minimal hardware overhead.

Approximate computing is emerging as a new paradigm to improve digital circuit performance by relaxing the requirement of performing exact calculations. Approximate adders rely on the idea that for uniformly distributed inputs, long carry-propagation chains are rarely activated. Unfortunately, however, the above assumption on input signal statistics is not always verified; in this paper we focus on the case (often encountered in practical signal processing applications) when the inputs have a Gaussian distribution. We show that for Gaussian inputs the error probability of previously proposed approximate adders approaches 25% for low sigma values, which is much larger than the uniform case. On the basis of this analysis, we propose an approximate adder with a correction circuit that drastically reduces the error rate for Gaussian distributed operand s. In order to investigate the performance of our approach in a real application, simulated results for a simple audio processing system are reported. Implementation results in 65nm technology are also presented.

The generation of complex signal sources is important for test and validation of electronic systems. With reference to noise sources, commercial systems only provide white noise sources while the scientific literature only recently proposed circuits that generate programmable colored noise. This paper proposes a programmable colored noise generator that, while generating noise signals with features matching the state of the art, overcomes the previously proposed circuits in terms of speed (+10%) and logic resource occupation (−75%).