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In recent years, GaN has become a forefront wide bandgap semiconductor material for next-generation, energy-efficient power electronics. With its higher breakdown strength, faster switching speed and lower on-resistance, GaN power devices can convert power far more efficiently than Si-based devices. While its performance is commercially demonstrated, widespread GaN adoption requires a scalable and high-yielding manufacturable technology platform enabling economies of scale and a full spectrum of low-cost products such as lateral and vertical power switches extending from 100V to 1,200V and beyond, monolithic ICs and rectifiers. QROMIS’ disruptive commercial solution to high volume, low cost and scalable GaN device manufacturing has been steadily gaining traction, owing to unique properties of specially-designed CMOS fab-friendly and semi-spec substrate called “QST®” (QROMIS Substrate Technology) with a core having a thermal expansion that very closely matches the thermal expansion of the GaN/AlGaN epitaxial layers. QST® enables breakage-free high-volume manufacturing of standard semi-spec thickness 200mm GaN device wafers (scalable to 300mm), covering all GaN applications including 100V-to-1800V high performance power devices, RF devices, and display microLEDs. In this talk, the following status updates on 200mm QST®-based materials and device technologies will be presented: (1) commercial QST® substrate products, (2) commercial GaN-on-QST® epi-wafer products, including development studies on epi-wafers for 1,200V and beyond applications, (3) high-performance normally-off 650V p-GaN based GaN-on-QST® HEMT transistors & monolithic ICs (with integrated drivers and logic) fabricated in a CMOS fab and commercialization timelines, (4) 200mm GaN-on-QST® device foundry services for the industry players, and (5) initial high-performance GaN-on-QST® RF device results.

Lateral GaN-based p-n junction gated field effect transistor (LJFET) devices have been demonstrated on 200mm engineered substrates. The maximum current density was 200 mA/mm and threshold voltage was −30V. Large gate width devices (40mm) exhibited 800 mA current. The devices have blocking capability exceeding 1.1 kV.

While developers are making headway with GaN power devices and applications, the existing wafer sizes, yields, cost and performance scaling for both GaN switches and diodes have been limited for volume manufacturing ― creating obstacles for widespread GaN adoption with competitive cost structure thereby preventing access to much larger addressable markets. As the result of significant R&D and pilot-line validation, QROMIS’ groundbreaking and disruptive solution to high volume, low cost and scalable GaN manufacturing is a specially-designed CMOS fab-friendly substrate material called “QST®” (QROMIS Substrate Technology) which supports high quality GaN epitaxy layers (from a few microns to tens of microns thick, including enablement of free-standing GaN) and high performance power device designs thereby paving the way to create a robust GaN power business with large products portfolio (100V to 1,500V lateral or vertical switches, diodes, ICs and more), all manufactured on the same 8-inch or 12-inch production platform. In addition, QST® enables advanced GaN LED devices (e.g. wafer-level chip-scale package (WLCSP) emitters and micro-LEDs) and GaN RF electronics (e.g. vertical devices) which are key features for high volume manufacturing and foundry economics. In this talk, status updates on QST®-based materials and device technologies, and the products development work, covering 8-inch diameter 100V-to-1,500V GaN power switches and diodes, GaN LEDs, and GaN RF devices, will be presented. Also, a detailed review of the company’s volume manufacturing status and 8-inch GaN device wafer foundry services for the industry players, in partnership with Vanguard International Semiconductor and Micron Technology, will be discussed. Figure 1

Availability of high-quality, large diameter SiC wafers in quantity has bolstered the commercial application of and interest in both SiC- and nitride-based device technologies. Successful development of SiC devices requires low defect densities, which have been achieved only through significant advances in substrate and epitaxial layer quality. Cree has established viable materials technologies to attain these qualities on production wafers and further developments are imminent. Zero micropipe (ZMP) 100 mm 4HN-SiC substrates are commercially available and 1c dislocations densities were reduced to values as low as 175 cm-2. On these low defect substrates we have achieved repeatable production of thick epitaxial layers with defect densities of less than 1 cm-2 and as low as 0.2 cm-2. These accomplishments rely on precise monitoring of both material and manufacturing induced defects. Selective etch techniques and an optical surface analyzer is used to inspect these defects on our wafers. Results were verified by optical microscopy and x-ray topography.

Recent advances in PVT c-axis growth process have shown a path for eliminating micropipes in 4HN-SiC, leading to the demonstration of zero micropipe density 100 mm 4HN-SiC wafers. Combined techniques of KOH etching and cross-polarizer inspections were used to confirm the absence of micropipes. Crystal growth studies for 3-inch material with similar processes have demonstrated a 1c screw dislocation median density of 175 cm-2, compared to typical densities of 2x103 to 4x103 cm-2 in current production wafers. These values were obtained through optical scanning analyzer methods and verified by x-ray topography.

The development of SiC bulk and epitaxial materials is reviewed with an emphasis on epitaxial growth using high-throughput, multi-wafer, vapor phase epitaxial (VPE) warm-wall planetary reactors. It will be shown how the recent emergence of low-cost high-quality 100-mm diameter epitaxial SiC wafers is enabling the economical production of advanced wide-bandgap Power–Switching devices.

Micropipe density (MPD) is a crucial parameter for silicon carbide (SiC) substrates that determines the quality, stability and yield of the semiconductor devices built on these substrates. The importance of MPD is underscored by the fact that all existing specifications for 6H- and 4H-SiC substrates set upper limits for it. Several methods for measuring the MPD are known, however, their reliability and applicability to various types of substrates (e.g. semiinsulating, conducting, etc.) has not been systematically studied. The subject of this paper is a comparative study of various techniques used for the MPD measurement accompanied by statistical analysis of the results. The study was initiated by several organizations working in the immediate field of silicon carbide or in closely related fields and included SiC substrate manufacturers, substrate consumers, equipment manufacturers and universities. The study represented a round robin experiment in which MPD was measured on thirty SiC wafers of various pedigrees. The values of MPD have been determined using both destructive and non-destructive techniques. The repeatability of each technique is analyzed and compared with that of other techniques.

The move towards commercialization of SiC based devices places increasing demands on the quality of the substrate material. While the industry has steadily decreased the micropipe (MP) levels in commercial SiC substrates over the past years, the achievement of wafers that are entirely free of MPs marks an important milestone in commercialization of SiC based devices. We present the results of a study for controlling the nucleation and propagation of MP defects in SiC ingots grown via PVT. Our studies confirm that during bulk growth of SiC, foreign polytype nucleation such as 3C-polytype occurs at the initial stages of growth (nucleation period) and/or during subsequent growth in the presence of facets. Results in this investigation suggest that polytype instability during crystal growth adversely impacts the MP density. Based on this key concept, growth conditions for nucleation and growth stages were optimized. These conditions were subsequently implemented in an innovative PVT growth environment to achieve a growth technique with highly effective polytype control. Under continuously modulated growth conditions, MPs induced by seed material and/or formed during the growth were eliminated. 2-inch and 3-inch diameter MP-free (zero MP density) conducting 4H-SiC ingots were obtained.

AlGaN/GaN high-electron-mobility transistor (HEMT) device layers were grown by metal organic chemical vapor deposition (MOCVD) on commercial engineered QST™ substrates to demonstrate a path to scalable, cost-effective foundry processing while supporting the thick epitaxial layers required for power HEMT structures. HEMT structures on 150 mm Si substrates were also evaluated. The HEMTs on engineered substrates exhibited material quality, DC performance, and forward blocking performance superior to those of the HEMT on Si. GaN device layers up to 15 µm were demonstrated with a wafer bow of 1 µm, representing the thickest films grown on 150-mm-diameter substrates with low bow to date.

In this paper, we investigate the role of grain boundaries in polycrystalline (Ba x Sr1−x )Ti1+y O3+z films, grown by metal organic vapor deposition, in the accommodation of nonstoichiometry, as well as their role in the strong composition dependence of the electric and dielectric behavior observed in these films. High-spatial resolution electron energy-loss spectroscopy is used for the analysis of composition and structural changes at grain boundaries, as a function of film composition. The existence of amorphous, titanium rich, TiO2-like phases at the grain boundaries of films with large amounts of excess Ti (y ≥ 0.08) may explain the non-monotonic resistance degradation behavior of the films as a function of Ti content. However, we show that a grain boundary phase model fails to explain the strong composition dependence of the dielectric behavior. Electron energy-loss spectra indicate a distortion of the Ti–O octahedra in the grain interiors in samples with increasing Ti excess. The decrease of the dielectric constant with increasing amounts of excess Ti is therefore more likely due to Ti accommodation in the grain interiors.

We have investigated the dielectric response of a series of {100} fiber-textured (BaxSr1−x)Ti1+yO3+z samples deposited by liquid-source metalorganic chemical vapor deposition onto Pt/SiO2/Si, as a function of the two most commonly varied microstructural parameters: film thickness and Ti nonstoichiometry y. We find that the overall behavior of these samples is adequately described by mean-field, Landau–Ginzburg–Devonshire theory as for bulk ferroelectrics. However, we quantify the impact of three separable factors for these films that greatly alter the dielectric susceptibility as a function of temperature, compared to that found for bulk ceramic samples at the same Ba/Sr ratio of 70/30: (i) Ti nonstoichiometry; (ii) the apparent interface effect; and (iii) the plane equibiaxial stress state resulting from thermal expansion mismatch strains. When these factors are properly taken into consideration, we show that these fine grained thin films behave in a manner entirely consistent with expectations based on ...

The electrical properties and surface morphologies of (Ba, Sr)TiO3 thin films, with various bottom electrode structures, deposited by liquid delivery metal organic chemical vapor deposition were investigated. Ir and Ru films as a bottom electrode with varying deposition temperatures were prepared onto SiO2 and polySi substrate structures using ion beam sputtering technique. It is observed that electrical properties of BST films deposited by liquid delivery MOCVD was changed with the deposition temperatures of Ir and Ru as well as substrate structures. Furthermore, it is revealed that these variations in leakage current could be strongly related with the roughness of BST films.

The resistance degradation behavior of Ba0.7Sr0.3TiO3 (BST) and SrTiO3 (ST) thin films is compared to the degradation behavior of titanate single crystals and ceramics with respect to the dependence on parameters such as temperature, thickness of the sample, applied voltage, acceptor dopant concentration and electrode material. Different model considerations to explain the resistance degradation in titanate thin films are discussed.

The temperature- and field-dependent permittivities of fiber-textured Ba0.7Sr0.3TiO3 thin films grown by liquid-source metalorganic chemical vapor deposition were investigated as a function of film thickness. These films display a nonlinear dielectric response under conditions representative of those encountered in dynamic random access memories or other integrated capacitor applications. This behavior has the exact form expected for a classical nonlinear, nonhysteretic dielectric, as described in terms of a power series expansion of the free energy in the polarization as in the Landau–Ginzburg–Devonshire approach. Curie–Weiss-like behavior is exhibited above the bulk Curie point (∼300 K), although the ferroelectric phase transition appears frustrated. Small-signal capacitance measurements of films with different thicknesses (24–160 nm) indicate that only the first term in the power series expansion varies significantly with film thickness or temperature. Possible origins for this thickness dependence are...

(Ba,Sr)TiO3 (BST) thin films grown by chemical vapor deposition and with platinum (Pt) top and bottom electrodes have been characterized with respect to the leakage current as a function of temperature and applied voltage. The data can be interpreted via a thermionic emission model. The Schottky approximation accounts for superohmic behavior at higher fields, but the barrier lowering is stronger than expected from this theory. While the leakage mechanism is comparable to SrTiO3 thin films prepared by chemical solution deposition, the absolute values of the leakage current are significantly lower for the metalorganic chemical vapor deposition (MOCVD) prepared BST film. This is presumably due to a more homogeneous microstructure of the latter and may also be due to different electrode processing. The influence of the film thickness on the leakage in combination with additional findings is used to discuss the field distribution in the films under a dc voltage stress.

An important application of ferroelectric films is their incorporation into dynamic random-access memories (DRAMs) as the storage node capacitor dielectric. Dynamic random-access memories represent a large market that is experiencing strong growth, but they are particularly significant as the technology leader for semiconductor devices. As products move to higher and higher integration density, new developments are first introduced in DRAMs. The steady trend toward higher density has placed severe demands on the device designs, particularly with respect to “squeezing” the capacitor into the available space.

Results presented here indicate a strong dependence between the surface roughness and its uniformity of epitaxial layers grown by chemical vapor deposition (CVD) and the underlying substrate dislocations and its domain structure. The substrates used were cut from boules grown by physical vapor deposition (PVT). The facet area and its borders were found to impact the CVD grown epitaxial layers. Epitaxial layers, 50 µm thick, were grown on 8° off-axis substrates. Substrates with and without micropipes were selected in order to investigate their impact on the epitaxy. Both wafers indicate a correlation between etch pit dislocation (EPD) density and surface roughness. However, the in general lower EPD density in the micropipe free wafer enhances the variation in surface roughness between different regions. The micropipe free substrate has an EPD equal to 1.3×104 cm−2 in the facet region, and the surface roughness, Ra, is 1.0 nm (2.98×2.32 mm2 area), while there is an increase both in EPD density and surface roughness in the close proximity corresponding to the border around the facet. Also thick epitaxial layers, 30 µm thick, were grown on near on-axis substrates, both C-face and Si-face, in order to investigate how the surface morphology develops with less influence from the step-flow growth mechanism. Both crystal directions are characterized by a three dimensional growth front surface similar as for PVT grown crystals in the facet region. The mix between step-flow and dislocation driven growth on near on-axis C-face chemical vapor deposition (CVD) grown epi-layers is resulting in a as smooth, and measured surface roughness is as low as for growth on 8° off-axis substrates.

Synthesis of high-purity, single-phase gallium nitride (GaN) powder has been achieved by reacting molten Ga with flowing ammonia (NH3) in a hot wall tube furnace. The optimum temperature, NH3 flow rate, and position of the boat in the hot wall tube furnace relative to the NH3 inlet for the complete reaction to pure GaN for our system were 975 °C, 400 standard cubic centimeters per minute (seem) and 50 cm, respectively. The X-ray diffraction (XRD) data revealed the GaN to be single phase with a = 3.1891 Å, c = 5.1855 Å, in space group P63mc, Z=2 and Dx =6.089 g cm−3. Scanning electron microscopy revealed a particle size distribution in the crushed material between 1 and 5 μm with most of the particles being ≍1 μm.

We have investigated the important failure mechanism of resistance degradation for polycrystalline MOCVD (Ba,Sr)TiO/sub 3/ thin films appropriate for use in DRAMs, as a function of voltage (field), thickness and temperature. At constant field, the measured degradation lifetime decreases with increasing film thickness, resulting from a decrease in the activation energy with respect to temperature for thicker films. Similarly, there are clear indications that thicker films are more field sensitive. Predicted resistance degradation lifetimes obtained from both temperature and voltage extrapolations for DRAM operating conditions of 85/spl deg/C and 1.6 V exceed the current benchmark of 10 years for all the films studied.

The strain state and its coupling to dielectric behavior have been investigated for {100} BST thin films deposited on Pt/SiO/sub 2//Si at 640/spl deg/C. It is estimated from X-ray diffraction that the in-plane biaxial strain is approximately 0.7%. We postulate that this is of sufficient magnitude to confine any spontaneous polarization to the plane of the film. The thickness-corrected dielectric behavior perpendicular to the substrate for these samples shows evidence of coupling to such an in-plane phase transition at approximately 390 K, as manifested by deviation from Curie-Weiss-like behavior at this temperature.

We have investigated the intrinsic resistance degradation behavior of fiber-textured MOCVD (Ba,Sr)TiO3 thin films appropriate for use in advanced DRAMs and integrated decoupling capacitors, as a function of applied voltage polarity, thickness, temperature, and dc bias/field. The results suggest that there is a significant stoichiometry effect on the measured resistance degradation lifetimes. The measured degradation lifetime increases as the Ti content is increased from 51.0 to 52.0 at%Ti, and then decreases with higher at%Ti. Predicted resistance degradation lifetimes obtained from both temperature and voltage extrapolations to DRAM operating conditions of 85°C and 1.6 V exceed the current benchmark of 10 years for all of the films studied.

We demonstrate the feasibility of a Ta2O5-based metal-insulator-metal (MIM) capacitor module which is integrated into the backend-of-the-line of a 0.5 μm CMOS process flow. The demonstration utilizes 6-inch wafers, sputtered Ta2O5 films with TaN and TiN electrodes, reactive ion etch (RIE) processes for defining the capacitor stack, and a metallization scheme which uses hot Al(Cu) and W plugs and a standard forming gas anneal (N2-5% H2). Acceptable electrical properties have been achieved within these processing constraints for the integrated MIM capacitor module, including specific capacitance (C/A) and leakage current density (J) of ≥ 5 fF/μm2 and ≤ 1 pA/pF-V, respectively. In addition, we compare the fundamental properties of the Ta2O5 dielectric with literature reports and point out that leakage mechanisms must be analyzed with care due to significant dielectric relaxation in the films under certain processing/measurement conditions. For the baseline integrated films, we confirm that leakage is most consistent with a Poole-Frenkel mechanism.

We have investigated the dielectric behavior of polycrystalline (Ba,Sr)TiO3 thin films deposited by liquid-source metalorganic chemical vapor deposition. The time-domain polarization current, the frequency dependence of the permittivity, and the dielectric loss for these CVD films are all described by a single set of parameters via the phenomenology of Curie - von Schweidler behavior. No change in the general form of the permittivity is found out to 1.5 GHz, suggesting that this description of the response is valid into the frequency range of interest for many applications. Low-frequency dispersion is found to be controllable, leading to films with very low dissipation factors and almost frequency-independent dielectric response. Finally, a non-zero intercept of the inverse of capacitance versus film thickness suggests the existence of a series interfacial capacitance, arising from either microstructural inhomogeneity or energy barriers to carrier transport at the film-electrode interfaces.

Temperature dependent Hall effect (TDH), low temperature photoluminescence (LTPL), secondary ion mass spectrometry (SIMS), optical admittance spectroscopy (OAS), and thermally stimulated current (TSC) measurements have been made on 6H-SiC grown by the physical vapor transport technique without intentional doping. n- and p-type as well semi-insulating samples were studied to explore the compensation mechanism in semi-insulating high purity SiC. Nitrogen and boron were found from TDH and SIMS measurements to be the dominant impurities that must be compensated to produce semi-insulating properties. The electrical activation energy of the semi-insulating sample determined from the dependence of the resistivity was 1.0eV. LTPL lines near 1.00 and 1.34eV, identified with the defects designated as UD-1 and UD-3, were observed in all three samples but the intensity of the UD-1 line was almost a factor of 10 more in the n-type sample than in the the p-type sample with that in the semi-insulating sample being inter...