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1. Uniform Spin Qubit Devices in an All-Silicon 300 mm Integrated Process

2. A flexible 300 mm integrated Si MOS platform for electron- and hole-spin qubits exploration

4. Molybdenum Nitride as a Scalable and Thermally Stable pWFM for CFET

5. FinFETs with Thermally Stable RMG Gate Stack for Future DRAM Peripheral Circuits

6. Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails

7. High Performance Thermally Resistant FinFETs DRAM Peripheral CMOS FinFETs with VTH Tunability for Future Memories

8. Solid state qubits: how learning from CMOS fabrication can speed-up progress in Quantum Computing

9. Uniform Spin Qubit Devices with Tunable Coupling in an All-Silicon 300 mm Integrated Process

10. A flexible 300 mm integrated Si MOS platform for electron- and hole-spin qubits exploration

11. TCAD-Assisted MultiPhysics Modeling & Simulation for Accelerating Silicon Quantum Dot Qubit Design

13. First Monolithic Integration of 3D Complementary FET (CFET) on 300mm Wafers

14. Buried Power Rail Integration with Si FinFETs for CMOS Scaling beyond the 5 nm Node

15. 3D Sequential Low Temperature Top Tier Devices using Dopant Activation with Excimer Laser Anneal and Strained Silicon as Performance Boosters

17. Buried power rail integration for CMOS scaling beyond the 3 nm node

19. Vertical Nanowire and Nanosheet FETs: Device Features, Novel Schemes for Improved Process Control and Enhanced Mobility, Potential for Faster & More Energy Efficient Circuits

20. Buried metal line compatible with 3D sequential integration for top tier planar devices dynamic Vth tuning and RF shielding applications

21. First Demonstration of 3D stacked Finfets at a 45nm fin pitch and 110nm gate pitch technology on 300mm wafers

22. 3-D Sequential Stacked Planar Devices Featuring Low-Temperature Replacement Metal Gate Junctionless Top Devices With Improved Reliability

24. 3D sequential stacked planar devices on 300 mm wafers featuring replacement metal gate junction-less top devices processed at 525°C with improved reliability

26. (Invited) Challenges on Surface Conditioning in 3D Device Architectures: Triple-Gate FinFETs, Gate-All-Around Lateral and Vertical Nanowire FETs

29. Temperature Dependence of the Band Gap of MnAgIn7S12 Single Crystals.

30. Challenges and opportunities of vertical FET devices using 3D circuit design layouts

31. Junctionless gate-all-around lateral and vertical nanowire FETs with simplified processing for advanced logic and analog/RF applications and scaled SRAM cells

32. (Invited) Vertical Nanowire FET Integration and Device Aspects

50. Relationship between annual volume of patients treated by admitting physician and mortality after acute myocardial infarction.

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