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A new low-jitter polyphase-filter-based frequency multiplier incorporating a phase error calibration circuit to reduce the phase errors is presented. Designing with a multiplication ratio of eight, it has been fabricated in a 0.13-[micro]m CMOS process. For input frequency of 25 MHz, the measured jitter is 2.46 ps (rms) and [+ or -] 9.33 ps (pk-pk) at 200-MHz output frequency, while achievable maximum static phase error of the calibration circuit is 2.4 ps. The calibration leads to the normalized rms jitter of 0.049%. Index Terms--Calibration, delay-locked loop (DLL), frequency multiplier, phase-locked loop (PLL), polyphase filter (PPF).

This paper presents a new fully integrated sensing interface and signal-conditioning application-specific integrated circuit (ASIC) for automotive accelerometers based on an 'injection-nulling switch' (INS) technique. The INS technique simplifies the design of both the switched-capacitor (SC) sensing amplifier and its supporting building blocks without jeopardizing its performance. This is done by counteracting the impact of charge injection and clock-feedthrough effects on sensitivity, resolution, and offset. It also decreases the number of opamps, capacitors, and switches being used. This results in reduction of power consumption, potential switching noise, and kT/C noise (sampled thermal noise which increases with the number of SC pairs being used) in the ASIC. A two-chip approach has been adopted in the implementation, with [+ or -]50 g sensing element and ASIC. The built-in trimming circuitry and signal-conditioning blocks, which includes a self-test circuit, are implemented internally to eliminate the need for external components. The experimental results have shown that the sensing system IC has achieved a power consumption of 10 mW (2 mA at 5 V), a maximum noise root spectral density of 11.87 [micro][V.sub.pk]/ [square root]Hz equivalent to rms noise root spectral density of 0.187 mg/[square root]Hz at 15.63 Hz, a signal-to-noise dynamic range of 77 dB for 500-Hz bandwidth and 74 dB for 1-kHz bandwidth based on 50 g, and a maximum clock noise of 1.562 mV. The die size of the ASIC is 2.8 mm x 2.3 nun using a standard 0.6-/[micro]m CMOS technology. Index Terms--Accelerometer, sensor, signal conditioning, switched-capacitor (SC) circuits.

This paper presents a new ion-sensitive field-effect transistor (ISFET) readout circuit including a novel nonlinear temperature compensation method that is based on the theoretical work for formulating a body-effect-based ISFET drain current expression, the derivation of an unified temperature-dependent ISFET threshold voltage expression, and the use of iterative method for solving design parameters in nonlinear equations. Regarding the basic readout circuit, it comprises only one source follower and one current source to establish a self-biased configuration for a single ISFET device. Due to elimination of body effect, it displays linear transfer characteristic in the experimental result. Incorporating temperature compensation further improves the thermal stability of the ISFET device in pH sensing function. This has been validated by the experimental results on pH values ranging from 4 to 9 in a temperature range of 22 [degrees]C to 50 [degrees]C from the measurement setup. The pH7 parameter is used as a reference in the method. The proposed works are attractive in terms of circuit simplicity, temperature-compensated performance, cost and compatibility for smart sensor operation. Index Terms--CMOS circuit, ion-sensitive field-effect transistor (ISFET) interface circuit, ISFET sensor, temperature compensation, zero temperature coefficient.

A new digital programmable CMOS analog front-end (AFE) IC for measuring electroencephalograph or electrocar-diogram signals in a portable instrumentation design approach is presented. This includes a new high-performance rail-to-rail instrumentation amplifier (IA) dedicated to the low-power AFE IC. The measurement results have shown that the proposed biomedical AFE IC, with a die size of 4.81 [mm.sup.2], achieves a maximum stable ac gain of 10 000 V/V, input-referred noise of 0.86 [micro] [V.sub.rms] (0.3 Hz-150 Hz), common-mode rejection ratio of at least 115 dB (0-1 kHz), input-referred dc offset of less than 60 [micro]V, input common mode range from -1.5 V to 1.3 V, and current drain of 485 [micro]A (excluding the power dissipation of external clock oscillator) at a [+ or -] 1.5-V supply using a standard 0.5-[micro]m CMOS process technology. Index Terms--Analog IC, biomedical circuits and systems, electrocardiogram (ECG), electroencephalograph (EEG), instrumentation amplifier (IA), rail-to-rail amplifier.

This paper presents the analysis of CMOS technology based nMOS source follower (NSF), pMOS source follower (PSF), and cascade-complementary source follower(CCSF) using a simplified large-signal model. Three new large-signal second harmonic equations and high-frequency transfer functions are derived. Optimization strategies which permit optimal design for low-distortion NSF, PSF, and CCSF are proposed. This includes a new complementary linearization method introduced for CCSF. With employment of dedicated optimization, the CCSF can achieve significantly better low-distortion broad-band characteristics than the other schemes. Comparative HSPICE simulated results for the three source followers have shown good agreement with the second-order analytical results using the simplified BSIM3 model equations. Index Terms--Buffer, CMOS circuit, harmonic distortion, large-signal model, linearization, source follower.

Background: Severe acute respiratory syndrome (SARS) became a worldwide outbreak with a mortality of 9.2%. This new human emergent infectious disease is dominated by severe lower respiratory illness and is [...]

An improved frequency compensation technique is presented in this paper. It is based on a cascade of a voltage amplifier and a transconductor to form a composite gain-enhanced feedforward stage in a two-stage amplifier so as to broaden the gain bandwidth via low-frequency pole-zero cancellation at heavy capacitive loads, but yet without increasing substantial power consumption. The technique has been confirmed by the experimental results. An operational amplifier has been designed to drive a capacitive load of 300 pF. The amplifier exhibits a dc gain of 87 dB, a gain bandwidth of 10.4 MHz at 63.7[degrees] phase margin, an average slew rate of 3.5 V/[micro]s, a compensation capacitor of only 6 pF while consuming 2.45 mW at a 3-V supply in a standard 0.6-[micro]m CMOS technology. Index Terms--Feedforward transconductance amplifier, frequency compensation, pole-zero cancellation, two-stage CMOS amplifier.