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Inspired by Mantis shrimp, this work aims to suggest a bottom-up approach for the fabrication of nanonetwork hydroxyapatite (HAp) thin film using self-assembled polystyrene

A huge shift in classical system integration composed of heterogeneous and homogeneous substances from 2D to 2.5D or even 3D assembly is a promising solution to satisfying the requirements of electronic packages, such as high operating speed, multifunctionality, and low form factor, under the physical limits of nanoscaled transistors and bottlenecks in related fabrication technologies. However, considerable dimension mismatch is introduced into the entire packaging by numerous microbumps ( ${\mu }$ -bumps) with complicated compositions in existing frameworks. In addition, failure location and precise reliability estimation are difficult to achieve when the layout of high-density ${\mu }$ -bump arrays is considered. To solve this urgent issue, an equivalent material characteristic methodology for ${\mu }$ -bump arrays based on finite element analysis (FEA) is developed in this study. A test vehicle for chip-on-chip packaging with wafer-level underfill is set up to obtain the mechanical characteristics of equivalent materials for the portion with internal ${\mu }$ -bump arrays. The equivalent plastic strain generation of the tin layer is simulated by systematically comparing the numerical convergence of FEA under the assumption that the lead-free solder forms ${\mu }$ -bumps within after the assembly process. Analytic results indicate that at least four rows of actual ${\mu }$ -bumps from the outermost edge of the ${\mu }$ -bump array are required to ensure numerical accuracy in contrast with the result obtained from the actual model of the present packaging structure.

An analytical model for the precise stress estimation of device channels is developed and demonstrated in this article. The resultant stress magnitude under considered stress resources, including strained source/drain (S/D) and intrinsic stressed shallow trench isolation (STI), is carefully predicted and compared. The calculated accuracy of the presented model is validated through finite element simulation by a given example of the Si/SiGe material system arranged in S/D local regions and surrounded in the STI field. The rapid prognosis ability of the proposed model is performed on Si, Ge, and group III–V channels of nano-scaled transistors under specifically designed stressors. The S/D dependence of performance variety for all considered device materials can be directly estimated by changing the designed S/D length substituted into the analytical model. Moreover, the variations in induced mobility gain are further quantified using stress-piezoresistance relation. The analytic results indicate that the strained Ge pMOSFET outperforms other strained devices, such as Si and In0.53Ga0.47As channel materials, while identically designed strained level resulting from the lattice mismatch of S/D stressors is considered. Furthermore, the unstrained GaAs-based nMOSFET integrated with lattice-matched S/D Ge, indicating its superior electron mobility as compared with the S/D strained Si and Ge nMOSFETs owing to its advanced initial mobility. Accordingly, the systematically analytic flow of stress-induced device performance prediction is demonstrated via the present analytical solution integrated with corresponding piezoresistance models.

Enhancing the mobility in metal-oxide-semiconductor field-effect transistors (MOSFETs) with narrow channel widths is highly sensitive to the stress effects of Si channel when related advanced strain engineering is introduced and is compatible with semiconductor processes. In practice, layouts have significant effect on the device performance, especially for the protruding gate width on shallow trench isolation structures. The geometric parameter is investigated by systematically analysing an n-channel MOSFET composed of silicon-carbon (SiC) stressors embedded in the source and drain (S/D) regions and a tensile contact etch stop layer (CESL) using three-dimensional finite element simulation. Tensile CESL (1.1 GPa) and a SiC S/D stressor with a carbon mole fraction of 1.65% are loaded on the structure. The difference in the interactive percentages between the mechanical bending effect of the CESL from the top of the poly gate and the downward force of the CESL adjacent to the spacer sidewall of the gate occurs when the protruding gate width is increased. Results indicate that mobility was highly enhanced by approximately 72.5% at a width of approximately 0.2 μm. The mechanical bending effect becomes dominant when the gate width is more than 0.2 μm. Consequently, the mobility gain decays and consequently converges toward a constant.

Given the increasing demand for power density and lightweight specifications, the discrete transistor outline-type package is no longer sufficient for personal vehicle. The new generation of high-power drive needs excellent heat dissipation and miniaturized system simultaneously. However, a traditional architecture of power module, direct bonding copper substrate, has serious warpage deformation and limitation of the heat dissipation. Therefore, a power module with an insulated metal substrate (IMS) is proposed. The proposed power module has a smaller volume, better electrical and thermal performance, and high reliability to be utilized in personal vehicles. A fine-quality assembly process is also presented and verified. Furthermore, two different kinds of molding materials that are widely used in power modules, silicone gel, and epoxy, are utilized. The IMS-type module with silicone gel molding fails the temperature cycling test (TCT) with the delamination of the solder layer. The module with epoxy successfully passes the automotive-grade reliability tests, including TCT, highly accelerated stress test, high-temperature reverse bias, and intermittent operational life test according to the standard of AEC-Q101. The finite element analysis for the IMS power module is presented and analyzed under the condition of TCT to estimate the mechanical behavior of the solder layer. The equivalent plastic strain of solder layer with silicone gel and epoxy is 0.76 and 0.08, respectively, after TCT, separately. The main reason can be attributed to the coefficient of thermal expansion between the IMS and molding material. According to the analyzed results, the effect of molding material should not be ignored in the power modulus.

To overcome the limited operational speed for nanoscaled transistors, scaling electronic devices to small and thin packaging and high-density arrangements have become the technological mainstream in designing versatile packaging architectures. Among these, a promising candidate is a three-dimensional integrated circuit (3D-IC) package due to its excellent capability of heterogeneous integration. However, sequential reliability is a troublesome concern given the complex packaging structure, especially for the assembly of microsolder joints. To address this issue, we propose a double-layered, thin stacked chip package under the application of temperature cycling load. The packaging warpage and creep impact of SnAg microsolder joints on their fatigue lifespan are examined separately. Nonlinear material/geometry finite element analysis (FEA) is used on important designed factors, including the elastic modulus of underfill, chip thickness, and the radius and pitch of through silicon via (TSV). The simulated results indicate that the best fatigue lifetime of SnAg microsolder joint can be achieved at 10 μm of each chip thickness, 230 μm and 5 μm for TSV pitch and radius within the examined designed extent. Moreover, a hard underfill material requires consideration when the mounted chips thicken. Consequently, reliability significantly improves by dispersing thermomechanical stress/strain of the SnAg microjoints to neighboring underfill and related packaging components, especially for large TSV array spacing.

Traditional heterogeneous integrated package structure actually uses several complete IC packages, while the final heterogeneous integrated package structure is completed by restacking and packaging of various IC packages. However, the relatively large package volume, low-density interconnections and low circuit density cannot meet the demand for lighter products. There are still many issues remained in the heterogeneous integration process due to the fact that each chip has its own chip size, material properties, and device type. In order to integrate various heterogeneous chips, a new chip stacking technology is necessary to simplify and reduce the packaging structure, which is used for multi-chip and multi-layer heterogeneous integrated packaging structures as well as obtaining high performance and high bandwidth density. A novel EIC (Embedded interposer carrier) heterogeneous integrated packaging technology is developed to provide SOC-like multi-layer and multi-chip stacking capabilities, which is similar to chiplet concept. In this work, a 21-mm × 14-mm interposer is embedded into an electric package, allowing the interposer to work as a bridge between the two chips, and to provide high-density and high-pin-count interconnects. The external dimension of these two chips is 9 mm × 9 mm and the chip thickness is 100µm. The electrical performance including the power integrity/signal integrity analysis was evaluated by designed test patterns. Daisy chain and Kelvin structure were also included in the testing structure. This new packaging structure is compatible with fan-out packaging technology and enables integration for different chips in order to achieve performance related to 3D IC with a low cost.

To meet the requirements of achieving high density and heterogeneous integrations, fan-out Panel level packaging (FOPLP) technology regarded as one of the promising alternative solutions has the capability of providing heterogeneous integrations, compared with fan-out Wafer level package (FOWLP), FOPLP enhances the usage ratio from FOWLP to reduce the fabricated cost. With Moore's Law, many reliability issues have occurred, warpage induced by coefficient thermal expansion (CTE) mismatch is the most urgent among these issues. In order to analyze the warpage mechanism, a FOPLP vehicle has been proposed in this study. The vehicle with multi-layer design is fabricated with a $510 \text{mm} \times 515 \text{mm}$ panel size and subsequently cut into 960 single packagings for assembly. The foregoing FOPLP structure with multiple redistribution layers (RDL) and dielectric layers is utilized to observe warpage. To achieve the target of predicting and controlling the warpage, the finite element method (FEM) is widely adopted. In finite element (FE) model, the complex structure should be simplified by using equivalent material approach to avoid scale mismatch. Following the warpage estimated by FEM is validated, this paper would analyze the warpage process-induced and provide the comment for improving the reliability of FOPLP.

Herein, we aim to develop a facile method for the fabrication of mechanical metamaterials from templated polymerization of thermosets including phenolic and epoxy resins using self-assembled block copolymer, polystyrene-polydimethylsiloxane with tripod network (gyroid), and tetrapod network (diamond) structures, as templates. Nanoindentation studies on the nanonetwork thermosets fabricated reveal enhanced energy dissipation from intrinsic brittle thermosets due to the deliberate structuring; the calculated energy dissipation for gyroid phenolic resins is 0.23 nJ whereas the one with diamond structure gives a value of 0.33 nJ. Consistently, the gyroid-structured epoxy gives a high energy dissipation value of 0.57 nJ, and the one with diamond structure could reach 0.78 nJ. These enhanced properties are attributed to the isotropic periodicity of the nanonetwork texture with plastic deformation, and the higher number of struts in the tetrapod diamond network in contrast to tripod gyroid, as confirmed by the finite element analysis.

In this study, tetraethyl orthosilicate-derived (TEOS-derived) siloxanes were successfully incorporated into chitosan (CS) membranes to form siloxane/CS mixed-matrix membranes (MMMs) via a drying-free and one-step process. Compared with the two-step process for the formation of MMMs in the previous literature, the one-step process of membrane preparation has the advantages of a decrease in the membrane formation time and the prevention of particle aggregation to form uniform and smooth MMMs. The siloxane/CS MMMs were used to separate a mixture of ethanol/water in the pervaporation process at 25 °C. MMMs with different siloxane concentrations, such as 0.025, 0.05, 0.15, 0.3 and 0.5 wt%, have been investigated, and MMMs with 0.05 wt% siloxanes (0.05 wt% MMMs) have the best pervaporation performance, with flux, separation factor and pervaporation separation index (PSI) values of 468 g/m2h, 2182 and 1021 kg/m2h, respectively. The pervaporation performance of 0.05 wt% siloxane/CS MMMs is better than that of CS-based membranes and other MMMs, as reported in the previous literature. As a result, the as-prepared siloxane/CS MMMs with 0.05 wt% siloxane loading show great potential for future industrial pervaporation applications.

A generalized solution for the bending stress/strain expression of flexible display composed of multi-stacked thin films is presented in this letter. Flexible display comprises an arbitrary number of films combined with dissimilar thicknesses and linear-elastic mechanical characteristics. Specific consequences for alternate layered systems are estimated to reveal the elementary trends of the dependencies of normalized bending strain and neutral axis (N.A.) position on the modulus and thickness ratios of the concerned layers. An actual architecture of flexible display is also provided as an example to calculate the results and is compared with the simulated predictions of finite element analysis. With various material selections of cover plate, the induced stresses on transparent conducting film and the position of the N.A. plate are separately investigated. Moreover, the impact of bending radius on the mechanical reliability of flexible encapsulation is also found. The presented results serve as a design guideline for the infrastructure optimization of flexible display devices without electrical failures.

The stress distributions and induced mobility gain in germanium (Ge)-based p-type MOSFETs (pMOSFETs) with an extended channel width are estimated in this paper. Several tin (Sn) concentrations of group-IV semiconductor GeSn alloys integrated with a compressive contact etching stop layer (CESL) are logically analyzed to evaluate the stress impact that results from the high lattice mismatch of embedded GeSn alloys on narrow device channels. Analytic results show that the stress intensity and corresponding mobility gain are enhanced by increasing the Sn concentration in the embedded source/drain GeSn stressors. By contrast, the performance variation of the short-channel Ge-based pMOSFET is strongly dominated by the extended width when the CESL covers the entire device. A mobility gain of up to ~124.07% is achieved for the 22-nm pMOSFET when a 100-nm extended width is considered. Moreover, the entire stress responses of high- ${k}$ /metal gate-last procedure combined with the following CESL deposition are investigated. Analytic results reveal that the stress relaxation along the channel height direction occurs after the poly gate etch process. Consequently, the adoption of a stressed CESL is demonstrated to be an effective approach to remedy the device mobility gain by stress improvement on the channel height direction.

This study uses the finite element analysis (FEA)-based atomistic-continuum method (ACM) combined with the Morse potential of metals to determine the effects of the elastic modulus (E) of a given example on atomic-level single-crystal copper (Cu). This work aims to overcome the estimated drawback of a molecular dynamic calculation applied to the mechanical response of macro in-plane-sized and atomic-level-thick metal-based surface coatings. The interactive energy of two Cu atoms within a face-centered metal lattice was described by a mechanical response of spring stiffness. Compared with the theoretical value, the parameters of the Morse potential dominated the predicted accuracy through the FEA-based ACM. Moreover, the analytic results indicated that the effective E of a single-crystal Cu was significantly sensitive to the given range of the interactive force field among atoms. The reliable elastic moduli of 86.8, 152.6, and 205.2 GPa along the Cu(100), Cu(110), and Cu(111) orientations of the Cu metal were separately acquired using the presented FEA-based ACM methodology.

Over the past two decades, the multi-functions of portable electronic devices have a significant influence to change the daily life of people. To meet the requirements of short transmission path of signals, and high I/O counts, ultrathin packaging technology and novel packaging architectures are continuously progressed in accordance with the emergence of advanced technologies in global semiconductor industry. Currently, the architecture of fan out panel-level packaging (FOPLP) grows into the mainstream to meet the essentials of three-dimensional chip stacking and heterogeneous integration. Some researches suggested that the fine metal trace small than 5μm/5μm (line-width/spacing) has been carried out by using redistributed layer (RDL) first interposer technology. In the meanwhile, the package on package framework was introduced for connecting application processor and stacked memory chips, which have been gradually implemented the above-mentioned portable electronic devices. However, the warpage issue of the top and bottom packages are always a critical issue while assembled. In order to solve this issue, an additional reinforcement frame, integrated with RDL interposer is proposed to reduce its deformation caused by coefficient of thermal expansion (CTE) mismatch among the materials of packaging components. The design of reinforcement frame is 15 mm x 15 mm with a 12 mm x 12 mm cavity. There are 540 interconnections with a 300 gm of pitch at the periphery of the present package. To estimate the reliability of abovementioned novel package with efficiency, a non-linear process-oriented finite element analysis (FEA) is approached. In addition, the technique of equivalent material characteristics is also needed into FEA model to simplify the complexity of packaging structure. Finally, the better combinations to control the warpage of the present novel packaging structure through choosing the type of MUF. The warpage of packaging is obtained via the simulation methodology and provided as the designed guideline of related packaging architectures.

Fan-out wafer/panel level package (FOWLP/ FOPLP) technology has been demonstrated widely in wearable electronics and flexible hybrid electronics (FHE). Previously, electromigration (EM) mainly has been discussed on the related FOWLP/FOPLP interconnect architecture design in the past researches. However, considering current or future complex application domain including automobile electronics or flexible design even free form, the interconnect not only has been considered EM but also thermomigration (TM) and stressmigration (SM). In this research, experiments have been designed for comparing main contribution among stress, temperature, and electrical effects for future applications such as portable electric products and (FHE).