94 results on '"Chao, Mango C.-T."'
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2. Rule Generation for Classifying SLT Failed Parts
3. A Reinforcement Learning Agent for Obstacle-Avoiding Rectilinear Steiner Tree Construction
4. Path-Based Pre-Routing Timing Prediction for Modern Very Large-Scale Integration Designs
5. Improving Cell-Aware Test for Intra-Cell Short Defects
6. Power distribution network generation for optimizing IR-drop aware timing
7. Test Methodology for Defect-based Bridge Faults
8. Layout-Based Dual-Cell-Aware Tests
9. A Model-Based-Random-Forest Framework for Predicting$V_{t}$Mean and Variance Based on Parallel$I_{d}$Measurement
10. DVFS Binning Using Machine-Learning Techniques
11. Generating Routing-Driven Power Distribution Networks With Machine-Learning Technique
12. Predicting Vt variation and static IR drop of ring oscillators using model-fitting techniques
13. Statistical methodology to identify optimal placement of on-chip process monitors for predicting fmax
14. A Model-Based-Random-Forest Framework for Predicting $V_{t}$ Mean and Variance Based on Parallel $I_{d}$ Measurement.
15. Statistical Framework and Built-In Self-Speed-Binning System for Speed Binning Using On-Chip Ring Oscillators
16. Generating Routing-Driven Power Distribution Networks with Machine-Learning Technique
17. Predicting Vt mean and variance from parallel Id measurement with model-fitting technique
18. Predicting Shot-Level SRAM Read/Write Margin Based on Measured Transistor Characteristics
19. Testing methods for quaternary content addressable memory using charge-sharing sensing scheme
20. Statistical techniques for predicting system-level failure using stress-test data
21. Random pattern generation for post-silicon validation of DDR3 SDRAM
22. Novel Circuit-Level Model for Gate Oxide Short and its Testing Method in SRAMs
23. Practical Routability-Driven Design Flow for Multilayer Power Networks Using Aluminum-Pad Layer
24. Testing methods for a write-assist disturbance-free dual-port SRAM
25. Power-switch routing for reducing dynamic IR drop in multi-domain MTCMOS designs
26. A process/device/circuit/system compatible simulation framework for poly-Si TFT based SRAM design
27. Power-Up Sequence Control for MTCMOS Designs
28. Fault Models and Test Methods for Subthreshold SRAMs
29. Testing strategies for a 9T sub-threshold SRAM
30. Testing Methodology of Embedded DRAMs
31. Alternate hammering test for application-specific DRAMs and an industrial case study
32. A Novel Test Flow for One-Time-Programming Applications of NROM Technology
33. Detecting stability faults in sub-threshold SRAMs
34. Design-for-debug layout adjustment for FIB probing and circuit editing
35. A Novel Pixel Design for AM-OLED Displays Using Nanocrystalline Silicon TFTs
36. A Novel Array-Based Test Methodology for Local Process Variation Monitoring
37. Testing methods for detecting stuck-open power switches in coarse-grain MTCMOS designs
38. Mathematical yield estimation for two-dimensional-redundancy memory arrays
39. Mask versus Schematic - an enhanced design-verification flow for first silicon success
40. Scan-Cell Reordering for Minimizing Scan-Shift Power Based on Nonspecified Test Cubes
41. Fault models and test methods for subthreshold SRAMs
42. Theoretical analysis for low-power test decompression using test-slice duplication
43. Power-switch routing for coarse-grain MTCMOS technologies
44. A novel test flow for one-time-programming applications of NROM technology
45. A novel array-based test methodology for local process variation monitoring
46. Fault models for embedded-DRAM macros
47. A metal-only-ECO solver for input-slew and output-loading violations
48. Scan-Chain Reordering for Minimizing Scan-Shift Power Based on Non-Specified Test Cubes
49. Unknown-tolerance analysis and test-quality control for test response compaction using space compactors
50. Investigation of gate oxide short in FinFETs and the test methods for FinFET SRAMs.
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