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In this work, a behavioral model for MOS Controlled-Thyristor (MCT) surge current analysis is proposed together with a design criterion. In this model, the relationships between the surge current characteristics including peak current (Ipeak) and high current rising rate (di/dt) of MCT and the device resistance (R) have been discussed, and then a readily measurable parameter, critical resistance (Rc), is presented to estimate the device surge current capability. According to the analytical results, both Ipeak and di/dt of MCT have been found to remain approximately constant with increasing resistance unless its resistance approaches and exceeds this Rc. It is therefore referred to as a design criterion for guiding the device design. The accuracy of the developed model and criterion are verified by comparing the obtained results with those resulting from simulation and experiment results.

An analysis model of the dV/dt capability for a metal—oxide—semiconductor (MOS) controlled thyristor (MCT) is developed. It is shown that, in addition to the P-well resistance reported previously, the existence of the OFF-FET channel resistance in the MCT may degrade the dV/dt capability. Lower P-well and N-well dosages in the MCT are useful in getting a lower threshold voltage of OFF-FET and then a higher dV/dt immunity. However, both dosages are restricted by the requirements for the blocking property and the forward conduction capability. Thus, a double variable lateral doping (DVLD) technique is proposed to realize a high dV/dt immunity without any sacrifice in other properties. The accuracy of the developed model is verified by comparing the obtained results with those from simulations. In addition, this DVLD MCT features mask-saving compared with the conventional MCT fabrication process. The excellent device performance, coupled with the simple fabrication, makes the proposed DVLP MCT a promising candidate for capacitor discharge applications.