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6 results on '"Chen, Chengguan"'

1. Pipelined BP Polar Decoder with a Novel Updated Scheme

Author

Zhang, Xiaojun, Li, Na, Li, Jun, Chen, Chengguan, Li, Hengzhong, Chen, Geng, Akan, Ozgur, Editorial Board Member, Bellavista, Paolo, Editorial Board Member, Cao, Jiannong, Editorial Board Member, Coulson, Geoffrey, Editorial Board Member, Dressler, Falko, Editorial Board Member, Ferrari, Domenico, Editorial Board Member, Gerla, Mario, Editorial Board Member, Kobayashi, Hisashi, Editorial Board Member, Palazzo, Sergio, Editorial Board Member, Sahni, Sartaj, Editorial Board Member, Shen, Xuemin (Sherman), Editorial Board Member, Stan, Mircea, Editorial Board Member, Jia, Xiaohua, Editorial Board Member, Zomaya, Albert Y., Editorial Board Member, Wu, Qihui, editor, Zhao, Kanglian, editor, and Ding, Xiaojin, editor

Published
2021
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3. A construction method of arbitrary-length polar codes

Author

Zhang, Xiaojun, Chen, Chengguan, Zhang, Rongcai, Cui, Jianming, and Zeng, Qingtian

Abstract

To remove the restriction on code length of polar codes, this paper proposes a construction scheme, called stepwise polar codes, which can generate arbitrary-length polar codes. The stepwise polar codes are generated by sub-polar codes with different code lengths. To improve coding performance, sub-polar codes are united by polarization effect priority algorithm, which can reduce the number of incompletely polarized channels. Then, the construction method of the generator matrix of the stepwise polar code is presented. Furthermore, we prove that the proposed scheme has lower decoding complexity than punctured, multi-kernel polar codes. Simulation results show that the proposed method can achieve similar decoding performance compared with the conventional punctured polar codes, rate-compatible punctured polar code, PC-short and asymmetric polar codes (APC) when code length N=48 and 72, respectively.

Published
2023
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6. Pipelined BP Polar Decoder with a Novel Updated Scheme

Author

Xiaojun Zhang, Li Na, Li Hengzhong, Jun Li, Chen Geng, and Chen Chengguan

Subjects
Very-large-scale integration, Scheme (programming language), Polar code, Computer science, Data_CODINGANDINFORMATIONTHEORY, Parallel computing, Throughput (business), computer, Decoder architecture, Decoding methods, computer.programming_language, Decoding latency, Scheduling (computing)
Abstract

Compared with the SC decoder, BP decoder provides a higher throughput and lower decoding latency for its inherent parallel nature. However, the functional units of existing BP decoders are not fully utilized. In this paper, we propose a new update scheduling scheme and hardware optimization design to improve the hardware efficiency of BP decoder. First, a pipelined decoder architecture is proposed to reduce the consumption of functional units. Then, a new update scheduling scheme is proposed, when updating the messages, both new-value and old-value approaches are used to improve the utilization of functional units and reduce the decoding latency. The analysis and synthesis results have shown that, compared with the existing methods, the proposed decoder suffers from a slight the decoding performance degradation, but the utilization rate of basic computational blocks (BCB) can be increased to 50.58%. The storage resource dissipation can be reduced by 20.1%–34.09%.

Published
2021

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