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5. Mechanism and improvement of on-resistance degradation induced by avalanche breakdown in lateral DMOS transistors

6. Device enhancement using process-strained-Si for sub-100-nm nMOSFET

7. The effect of geometry on the noise characterization of SiGe HBTs and optimized device sizes for the design of low-noise amplifiers

8. Channel width dependence of hot-carrier induced degradation in shallow trench isolated PMOSFET's

9. Modeling and characterization of electromigration failures under bidirectional current stress

17. An improvement on shallow trench isolation process

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