155 results on '"Chen, Xingbi"'
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2. Theory of an improved vertical power MOSFET using high-k insulator
3. Study on HK-VDMOS with Deep Trench Termination
4. Increasing breakdown voltage of LDMOST using buried layer
5. A Novel No Miller Plateau SOI-LIGBT With Low Saturation Current and Improved Switching Performance
6. A Novel Double-RESURF SOI-LIGBT With Improved $V_{\mathrm{\scriptscriptstyle ON}}-{E}_{ \mathrm{\scriptscriptstyle OFF}}$ Tradeoff and Low Saturation Current
7. A Novel Diode-Clamped Carrier Stored Trench IGBT With Improved Performances
8. A Novel Low on-State Voltage SOI LIGBT With Enhanced Conductivity Modulation
9. A Novel Low Channel Resistance LDMOS with Planar and Trench Gates
10. Simulation study of a novel thin layer SOI carrier-stored TLIGBT with self-biased pMOS
11. Simulation Study of Trench IGBT with Diode-Clamped P-Well for High dI/dt and dV/dt Controllability
12. Study on Conductivity Degradation of High-k VDMOS Caused by Ferroelectricity
13. Simulation Study on Novel High Voltage Transient Voltage Suppression Diodes
14. Simulation study on a novel snapback-free and low turn-off loss reverse-conducting SOI-LIGBT with P-type double trench gates on the anode region
15. A Novel Fast-Switching SOI LIGBT with Anode Junction Paralleled by a Diode
16. An Ultra-Low On-Resistance Triple RESURF Tri-Gate LDMOS Power Device
17. A New Carrier Stored Trench IGBT Realizing Both Ultra Low $V_{\text{on}}$ and Turn-off loss
18. A Positive Low-Voltage Power Supply Integrated With High-Voltage Devices
19. A High Speed High Voltage Normally-off SiC Vertical JFET Power Device
20. A 600-V Super-Junction pLDMOS Utilizing Electron Current to Enhance Current Capability
21. Simulation Study of a Low ON-State Voltage and Saturation Current TCIGBT With Diodes
22. A novel snapback-free reverse-conducting (RC) SOI-LIGBT with a built-in thyristor
23. An Novel Thin Layer SOI Carrier-Stored Trench LIGBT With Enhanced Emitter Injection
24. An improved SOI trench LDMOST with double vertical high-k insulator pillars
25. Simulation design and development of double thimble type fiber Bragg grating temperature sensor
26. A Novel Double-RESURF SOI-LIGBT With Improved VON-EOFF Tradeoff and Low Saturation Current.
27. A TIGBT With Floating n-Well Region for High dV/dt Controllability and Low EMI Noise
28. A low on-state voltage TIGBT with planar gate self-biased pMOS
29. A novel level-shifter integrated on the edge termination region of the high voltage device
30. Low on‐state voltage and saturation current Trench Insulated Gate Bipolar Transistor with integrated Zener diode
31. A novel CMOS positive to negative voltage converter and regulator
32. A novel SCR-LDMOS for high voltage ESD protection
33. A 300-V Ultra-Low-Specific On-Resistance High-Side p-LDMOS With Auto-Biased n-LDMOS for SPIC
34. A new low specific on-resistance H k -LDMOS with N-poly diode
35. A Low On-State Voltage and Saturation Current TIGBT With Self-Biased pMOS
36. A novel diode-clamped CSTBT with ultra-low on-state voltage and saturation current
37. Study on a novel junction edge termination for HK-MOSFET
38. An LDMOS with large SOA and low specific on-resistance
39. Deep trench junction termination employing variable-K dielectric for high voltage devices
40. Vertical power Schottky barrier diodes using a high-k insulator
41. A superjunction structure using high-kinsulator for power devices: theory and optimization
42. A new super-junction VDMOS realizing fast reverse recovery
43. A New Solution for Superjunction Lateral Double Diffused MOSFET by Using Deep Drain Diffusion and Field Plates
44. An Improved Superjunction Structure With Variation Vertical Doping Profile
45. Simulation design and development of double thimble type fiber Bragg grating temperature sensor
46. Study on H K -VDMOS with Deep Trench Termination
47. Study on layouts design of the voltage sustaining layer using high-k insulator
48. Novel technique for lateral high‐voltage totem‐pole power devices
49. A novel self-generated low-voltage power supply for the gate-driver of high-voltage off-line SMPS
50. A variation laterl doping layer and lightly doped region compensated superjunction LDMOS.
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