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This paper investigates the meso-damage mechanism and the cracking characteristics of rock and soil aggregate (RSA) by X-ray computed tomography (CT) under uniaxial compressive loading. Cylindrical RSA specimens (50 mm diameter and 100 mm height) with rock percentage 40 % were produced to perform a series of uniaxial compressive strength test. The damage cracking characteristic is identified by the mean CT value, and also the meso-damage propagation law is analyzed based on the damage factor defined by the CT value. From the test results, the variation of CT value for region of interest is different at the same stress level, the mean CT value for the RSA specimen, and rock block inclusions, and their adjacent soil regions decrease with the increasing stress level. It is more sensitive for block inclusions than soil regions. Also, the meso-damage evolution equation and constitutive equation for RSA are established. The estimated result is in agreement with the measured result. Moreover, based on the image threshold segmentation method, length, area, and mean width of cracks obey to power function distribution. Crack statistical characteristics are closely related to the rock block’s distribution and morphology. These results confirm that the elastic mismatch of RSA is the primary reason resulting in cracking under loading, damage characteristics of RSA is progressive, cracking begins from rock–soil interfaces, and then propagate into soil matrix.

Photon trapping photodiode design in HgCdTe mid-wavelength infrared focal plane array detectors is investigated in this work, utilizing the finite-difference time-domain technique. The quantum efficiency and the current–voltage characteristics have been numerically simulated, using Crosslight Technology Computer Aided Design software. Simulation results indicate that dark current is reduced more significantly in the photon trapping photodiode than in the mesa photodiode while maintaining the same quantum efficiency.

Spectral crosstalk suppressing design of two-color HgCdTe medium-wave/long-wave (MW/LW) $$\hbox {n}^{+}$$ – $$\hbox {p}_{1}$$ – $$\hbox {P}_{2}$$ – $$\hbox {P}_{3}$$ – $$\hbox {N}^{+}$$ infrared focal plane arrays (IRFPAs) detector functioning in simultaneous mode is carried out in this study, using Crosslight Technology Computer Aided Design (TCAD) software. A compositional barrier of $$\hbox {P}_{2}$$ -region sandwiched between LW absorption layer of $$\hbox {p}_{1}$$ -region and MW absorption layer of $$\hbox {P}_{3}$$ -region is designed to suppress spectral crosstalk. MW-to-LW crosstalk can be significantly suppressed to 2.1 % while LW-to-MW crosstalk can be maintained less than 1 % by integrating an optimized compositional barrier.

A multiple mask technique, integrating patterned silicon dioxide (SiO2) film over patterned thick photoresist (PR) film, has been investigated as a method to perform mesa etching for device delineation and electrical isolation of mercury cadmium telluride (HgCdTe) third-generation infrared focal-plane arrays. The multiple mask technique was achieved by standard thick PR photolithography, SiO2 film deposition to cover the thick PR patterned film, and etching the SiO2 film at the bottom region after another photolithography process. The dynamic resistance in the zero-bias and low-reverse-bias regions of HgCdTe photodiode arrays isolated by inductively coupled plasma (ICP) etching with the multiple mask of patterned SiO2 and patterned thick PR film underneath was improved one- to twofold compared with a simple mask of patterned SiO2. It is suggested that the multiple mask technique is capable of maintaining high etching selectivity while reducing the side-wall processing-induced damage of ICP-etched HgCdTe trenches. The results show that the multiple mask technique is readily available and shows great promise for etching HgCdTe mesa arrays.

A novel mask technique utilizing patterned silicon dioxide films has been exploited to perform mesa etching for device delineation and electrical isolation of HgCdTe third-generation infrared focal-plane arrays (IRFPAs). High-density silicon dioxide films were deposited at temperature of 80°C, and a procedure for patterning and etching of HgCdTe was developed by standard photolithography and wet chemical etching. Scanning electron microscopy (SEM) showed that the surfaces of inductively coupled plasma (ICP) etched samples were quite clean and smooth. Root-mean-square (RMS) roughness characterized by atomic force microscopy (AFM) was less than 1.5 nm. The etching selectivity between a silicon dioxide film and HgCdTe in the samples masked with patterned silicon dioxide films was greater than 30:1. These results show that the new masking technique is readily available and promising for HgCdTe mesa etching.

A modified postannealing at 1000 °C in N2 ambient has been carried out to improve the Ge distribution in the SiGe layer fabricated by the Ge condensation process, which is a potential technique for strained Si fabrication. Three kinds of SiGe-on-insulator samples have been fabricated by so-called Ge condensation, which is the oxidation of the SiGe layer on an insulator to enhance the Ge fraction. After different postannealing processes and the necessary cleaning steps, 20-nm-thick strained Si films are epitaxially grown on them. Though the differences of surface topography among the three samples are not great, the one with the modified postannealing process has the most uniform Ge element distribution and the least misfit dislocations. Meanwhile, the strain values obtained by Raman spectra are coherent with the Ge fraction in SiGe near the Si/SiGe interface and the sample with the modified postannealing process has a larger strain value than the one with a conventional postannealing. The performance of m...

Wafer bonding and layer transfer are two fundamental technologies in the fabrication of advanced microsystems. In the authors’ experiments, prior to Ge wafer bonding, the hydrophilicity of the germanium surface after wet chemical treatment and O2/N2 plasma activation is evaluated by contact angle measurement. The effects and mechanism of wet or dry treatments on the Ge surface roughness are also characterized. The results are used to tailor the Ge–SiO2 direct bonding process. Finally, oxygen plasma activation for 10 s and B+/H+ coimplantation are employed to facilitate Ge–SiO2 direct bonding and Ge layer transfer at a low temperature. In comparison with hydrogen only ion implantation using the same fluence, coimplantation of B+ and H+ decreases the layer transfer temperature from over 400–320 °C.

In order to evaluate the strain stability, arrays of strained Si/SiGe nano-stripes and nano-pillars were fabricated by Electron-Beam Lithography (EBL) and Reactive-Ion Etching (RIE). The strain relaxation in the patterned strained Si on SiGe-on-insulator (SGOI) was investigated by high-resolution UV micro-Raman spectroscopy. The Raman measurements before and after patterning indicate that most of the strain in the top strained Si is maintained until scaling down to 300 nm, and relaxation of

Room-temperature bonding between low-pressure chemical vapor deposition (LPCVD) oxide and silicon has been achieved by using N + plasma activation and chemical mechanical polishing (CMP). The bonding energy reaches the value of bulk silicon fracture energy (about 2.5 J/m 2 ) after annealing at 400 °C for an hour, which is higher than the bonding energy between thermal oxide and silicon using the same process. The density difference is believed to be the main contributor to the enhanced bonding energy. Silicon-on-insulator (SOI) substrate is fabricated using Smart-Cut technology and then chemical mechanically polished to obtain a reasonably smooth surface for device manufacture. This low-temperature bonding process can be used in many applications, such as microelectromechanical systems (MEMS) and three-dimensional integration.

A SiGe-on-insulator (SGOI) structure with high Ge content and low density of dislocations is fabricated by a modified Ge condensation technique. The formation and elimination of stacking faults during condensation process are analyzed by transmission electron microscopy. A Si 0.19 Ge 0.81 OI substrate is fabricated utilizing two steps of oxidation and intermittent annealing. The time of oxidation or annealing at 900 °C is essential for the elimination of stacking faults in high Ge content SGOI substrate. The surface morphology of SGOI is investigated by atomic force microscopy and the defect density is evaluated from wet etching method. After the final condensation, the surface root-mean-square roughness (rms) of SiGe layer is kept below 1 nm and the threading defect density is controlled around 10 4 cm −2 . The smooth surface and integrated lattice structure of SiGe layer indicate that the SGOI is suitable for heteroepitaxial growth of strained Ge, GaAs and III–V compounds.

In this paper, two approaches combined the Separation by IMplanted OXygen (SIMOX) layer transfer (SLT) process with Si epitaxy are proposed to fabricate thick-film Silicon-on-Insulator (SOI). Spectroscopic ellipsometry indicates thick-film SOI wafers with the top Si layers of 1430.86 {plus minus} 19.8 nm and 1476.44 {plus minus} 18.5 nm are achieved. Atomic-scale sharp interfaces between the top Si layer and buried oxide layers are observed by high-resolution transmission electron microscopy. Using atomic force microscopy, surface morphology of the SOI wafer is also investigated.

We have investigated the growth of InAs/GaSb type-II superlattices by gas-source molecular-beam epitaxy, where Sb cracker cell and AH 3 high-temperature injector are used to provide Sb and As flux, respectively. Sharp InAs/GaSb interfaces can be obtained at optimized growth conditions, revealed by high-resolution transmission electron microscopy. Moreover, it was found that the intrinsic net tensile strain of the InAs/GaSb superlattices can be partially compensated by intentional insertion of a sub-monolayer InSb layer at the interfaces of InAs and GaSb. Finally, based on InAs/GaSb superlattices grown by gas-source molecular-beam epitaxy (GSMBE), we have fabricated a photodiode with cut-off wavelength of 4.9 μm.

Silicon-on-Insulator (SOI) substrates incorporated with buried MoSi 2 were fabricated using room temperature plasma bonding technology and smart cut technology. The molybdenum disilicide phase formation and morphology were studied by means of four-point probe measurements, X-ray diffraction analysis, atomic force microscopy and transmission electron microscopy examination. It is found that the transition of high-resistance phase Mo 3 Si to low-resistance phase h-MoSi 2 occurs at approximately 750 °C. The t-MoSi 2 phase emerges at approximately 900 °C. SOI substrate incorporated with buried silicide layer of complete t-MoSi 2 phase can be achieved by 900 °C annealing for 20 min.

Bonded silicon-on-insulator (SOI) materials via the Smart-cut^T^M (or ion-cut) process attract increasing interests due to their great capability and versatility in fabricating novel virtual substrates. Previously we reported the successful fabrication of silicon-on-aluminum-nitride (SOAN) structure with smart-cut process [C.L. Men, Z. Xu, Z. An, X.Y. Xie, M. Zhang, C.L. Lin, Physica B 324 (2002) 229]. In this work, we characterize the bonded SOAN structure with Rutherford backscattering spectroscopy (RBS), transmission electron microscopy (TEM) together with Kikuchi line diffraction patterns, and high resolution X-ray diffraction (HRXRD) techniques. It is found that, after smart-cut process, the top Si layer preserves a rather good single crystalline quality, while strain is induced in top Si and can be altered in the annealing step. The rotational misalignment during bonding step can be evaluated by Kikuchi line patterns. Our discussions here may be common for all bonded virtual substrates via smart-cut technology.

Dual-band HgCdTe IRFPAs are one of the most important developing frontiers for 3rd generation IRFPAs. A barrier has been implemented in the dual-band HgCdTe detectors to overcome the electrical cross-talk between two layers with different compositions. Moreover, we now reveal another benefit of this barrier structure. This barrier can relieve the critical demands in photo-lithography of the implantation process, which shows great advantages as the dimension of a single element in an advanced dual-band IRFPAs is becoming less than 30μm. When the implantation pattern migrates about 2μm, the profile in the dual-band structure is exposed under implantation. An n-type connection between LW layer and MW layer will be created. Without a barrier, the dark current of the MW layer is completely ruined by fractions from the LW layer. While a modified barrier is utilized, the dark current can be restrained to the same order as those with perfect implantation.

The structural and electrical characteristics of a novel nanolaminate Al2O3/ZrO2/Al2O3 high-k gate stack together with the interfacial layer (IL) formed on SiGe-on-insulator (SGOI) substrate have been investigated. A clear layered Al2O3 (2.5 nm)/ZrO2 (4.5 nm)/Al2O3 (2.5 nm) structure and an IL (2.5 nm) are observed by high-resolution transmission electron microscopy. X-ray photoelectron spectroscopy measurements indicate that the IL contains Al-silicate without Ge atom incorporation. A well-behaved C–V behavior with no hysteresis shows the absence of Ge pileup or Ge segregation at the gate stack/SiGe interface.

A metal-insulator-semiconductor (MIS) structure containing an HfO 2 /SiO 2 stack tunnel layer, isolated Germanium (Ge) nanocrystals, and an HfO 2 capping layer, was obtained by an electron-beam evaporation method. A high-resolution transmission electron microscopy (HRTEM) study revealed that uniform and pronounced Ge nanocrystals had formed after annealing. Raman spectroscopy provided evidence for the formation of Ge-Ge bonds and the optimal annealing temperature for the crystallization ratio of the Ge. The electric properties of the MIS structure were characterized by capacitance-voltage (C-V) and current-voltage (I-V) measurements at room temperature. Negative photoconductivity was observed when the structure was under a forward bias, which screened the bias voltage, resulting in a decrease in the current at a given voltage and a negative shift in flat band voltage. A relatively high stored charge density of 3.27×10 12 cm -2 was also achieved.

Aluminum nitride (AlN) thin films have attracted interests as the buried dielectric layer in silicon-on-insulator (SOI) substrates. The precondition for this application is that AlN films have smooth surfaces for wafer bonding and excellent insulation properties. In this work, AlN films synthesized by pulsed-laser deposition (PLD) and ion-beam-enhanced deposition (IBED) techniques are compared under the concern of their suitability for SOI application. Both PLD-deposited and IBED-deposited AlN films exhibit smooth surface morphologies. However, AlN films show quite different electrical properties due to different microstructures: microcrystalline wurtzite by PLD but amorphous by IBED. PLD AlN films have high leakage current and high dynamic charge densities. In contrast, IBED films have low leakage current and the breakdown field is about 2.1 MV/cm. Moreover, after postannealing at 800–1100 °C, the breakdown field exceeds 4 MV/cm and the leakage current is reduced nearly two orders in magnitude. We conclude that IBED is more suitable technique to fabricate AlN films as buried insulators in SOI substrates.

Ultra-long rutile tin dioxide nanowires and nanobelts are synthesized by thermal oxidation of tin powder using gold film as the catalyst. Nanowire or nanobelts can be selectively produced by tuning the reaction temperature. The vapour-liquid-solid growth mechanism is proposed. The band gaps of the nanowires and nanobelts are 3.74 and 3.81 eV respectively, determined from UV/visible absorption spectral results. The SnO2 nanowires show stable photoluminescence with two emission peaks centred at around 470 and 560 nm. Their wavelengths stay almost fixed while their intensities depend sensitively on the temperatures within the examination ranges from 10 to 300 K. The SnO2 nanobelts show similar photoluminescence behaviours and the origin of the luminescence is discussed.

A metal-insulator-semiconductor (MIS) structure containing an HfO2/SiO2 stack tunnel layer, isolated Germanium (Ge) nanocrystals, and an HfO2 capping layer, was obtained by an electron-beam evaporation method. A high-resolution transmission electron microscopy (HRTEM) study revealed that uniform and pronounced Ge nanocrystals had formed after annealing. Raman spectroscopy provided evidence for the formation of Ge–Ge bonds and the optimal annealing temperature for the crystallization ratio of the Ge. The electric properties of the MIS structure were characterized by capacitance-voltage (C-V) and current–voltage (I–V) measurements at room temperature. Negative photoconductivity was observed when the structure was under a forward bias, which screened the bias voltage, resulting in a decrease in the current at a given voltage and a negative shift in flat band voltage. A relatively high stored charge density of 3.27 × 1012 cm−2 was also achieved.

An improved technique is demonstrated to fabricate silicon–germanium on insulator (SGOI) starting with a sandwiched structure of Si/SiGe/Si. After oxidation of the sandwiched structure and successive annealing, a relaxed SiGe-on-insulator (SGOI) structure is produced. Our results indicate that the added Si cap layer is advantageous in suppressing Ge loss at the initial stage of SiGe oxidation and the subsequent annealing process homogenizes the Ge fraction. Raman measurements reveal that the strain in the SiGe layer is fully relaxed at high oxidation temperature (∼1150 ◦ C) without generating any threading dislocations and crosshatch patterns, which generally exist in the relaxed SiGe layer on bulk Si substrate.

Relaxed SiGe-on-Insulator (SGOI) is fabricated using a modified fabrication technique based on Ge condensation by oxidizing the SiGe layer on SOI. In this procedure, the Ge atoms are condensed into the remaining SiGe layer due to the rejection of Ge atoms from the oxide layer and the large diffusion coefficient of Ge in SiGe. Raman measurements reveal that the strain in the SiGe layer is fully relaxed at high oxidation temperature (� 11501C). Atomic force microscopy (AFM) and transmission electron microscopy (TEM) results indicate that no dislocation is introduced for strain relaxation during the oxidation process. The strain relaxation is explained by a relaxation model involving a compliant substrate, on which the SiGe layer expands laterally via an ultra-low viscosity slippage plane at the SiGe/ buried oxide (BOX) interface. r 2005 Elsevier B.V. All rights reserved.

A fully depleted SiGe-on-insulator (SGOI) substrate has been fabricated by a modified Ge condensation technique. The characteristics of the SiGe/ buried-oxide (BOX) interface and the influence on the electrical performance of the SGOI substrate are investigated. The long oxidation time during the fabrication of the fully depleted (FD) SGOI substrate leads to Ge atom pileup at the SiGe/BOX interface, and consequently a large number of interfacial trapped charges are produced. Furthermore, our results disclose that Ge diffusion into the BOX increases the interfacial trapped charges and the fixed oxide charges during oxidation. As a result, the electrical properties of the FD-SGOI substrate degrade due to the poor SiGe/BOX interface.

Aluminum nitride (AlN) thin films prepared by ion beam enhanced deposition (IBED) have desirable properties as the buried dielectric in silicon-on-insulator substrates. In this work, the electrical properties of IBED deposited AlN films were investigated. Our results show that the electrical properties of AlN films deteriorate with increasing Al evaporation rate. The film deposited at a deposition rate of 0.05 nm/s exhibits good insulating properties and its breakdown field is 2.1 MV/cm. After thermal treatment, the breakdown field exceeds 4 MV/cm and the leakage current is reduced about 60 times. Capacitance–Voltage (C–V) results corroborate that the AlN film possesses an extremely low density of trapped charges. However, the density of the interfacial states inside the bandgap is relatively high in the non-abrupt AlN/Si interface region but they can be partially reduced by high-temperature annealing. D 2004 Elsevier B.V. All rights reserved.

The application of silicon-on-insulator (SOI) substrates to high-power integrated circuits is hampered by self-heating effects due to the poor thermal conductivity of the buried SiO 2 layer. We propose to replace the buried SiO 2 layer in SOI with a plasma synthesized SiO x N y thin film to mitigate the self-heating effects. The SiO x N y films synthesized on silicon by plasma immersion ion implantation (PIII) exhibit outstanding surface topography, and excellent insulating characteristics are maintained up to an annealing temperature of 1100 °C. Hence, the polycrystallization in our SiO x N y materials is insignificant during conventional complementary metal oxide silicon (CMOS) processing. Using Si/SiO x N y direct bonding and the hydrogen-induced layer transfer, a silicon-on-SiO x N y structure has been successfully fabricated. Cross-sectional high-resolution transmission electron microscopy (HRTEM) and spreading resistance profiling (SRP) reveal that the bonded interface is abrupt and the top Si layer exhibits nearly perfect single crystalline quality. The reaction mechanism of SiO x N y and Si wafer bonding are also discussed.

Al2O3–ZrO2 composite films were fabricated on Si by ultrahigh vacuum electron-beam coevaporation. The crystallization temperature, surface morphology, structural characteristics and electrical properties of the annealed films are investigated. Our results indicate that the amorphous and mixed structure is maintained up to an annealing temperature of 900 8C, which is much higher than that of pure ZrO2 film, and the interfacial oxide layer thickness does not increase after annealing at 900 8C. However, a portion of the Al2O3–ZrO2 film becomes polycrystalline after 1000 8C annealing and interfacial broadening is observed. Possible explanations are given to explain our observations. A dielectric constant of 20.1 is calculated from the 900 8C-annealed ZrO2–Al2O3 film based on high-frequency capacitance–voltage measurements. This dielectric characteristic shows an equivalent oxide thickness (EOT) as low as 1.94 nm. An extremely low leakage current density of ~210 7 A/cm 2 at a gate voltage of 1 V and low interface state density are also observed in the dielectric film.

We propose to replace the buried SiO2 layer in silicon-on-insulator (SOI) with a plasma-synthesized AlN thin film to mitigate the selfheating penalty. The AlN films synthesized on Si by metal plasma immersion ion implantation–deposition (Me-PIIID) exhibit outstanding surface topography and excellent insulating characteristics. Using direct bonding process and the hydrogen-induced layer transfer method, a silicon-on-AlN (SOAN) structure has been successfully fabricated. Cross-sectional high-resolution transmission electron microscopy (HRTEM), X-ray photoelectron spectroscopy (XPS) depth profiles and spreading resistance probe (SRP) reveal that a uniform buried AlN layer is under a single crystal Si overlayer. The interfaces between the top Si layer, buried AlN layer, and Si substrate are smooth and sharp. In addition, the new SOAN device has been verified in two-dimensional device simulation and demonstrates that the self-heating penalty of SOI can indeed be reduced using SOAN substrates. D 2004 Elsevier B.V. All rights reserved.

Zr0.6Al0.4O1.8 dielectric films were deposited directly on strained SiGe substrates at room temperature by ultra-high vacuum electron-beam evaporation (UHV-EBE) and then annealed in N2 under various temperatures. X-ray diffraction (XRD) reveals that the onset crystallization temperature of the Zr0.6Al0.4O1.8 film is about 900 °C, 400 °C higher than that of pure ZrO2. The amorphous Zr0.6Al0.4O1.8 film with a physical thickness of ∼12 nm and an amorphous interfacial layer (IL) with a physical thickness of ∼3 nm have been observed by high-resolution transmission electron microscopy (HRTEM). In addition, it is demonstrated there is no undesirable amorphous phase separation during annealing at temperatures below and equal to 800 °C in the Zr0.6Al0.4O1.8 film. The chemical composition of the Zr0.6Al0.4O1.8 film has been studied using secondary ion mass spectroscopy (SIMS).

The application of silicon-on-insulator (SOI) substrates to high-power integrated circuits is hampered by the self-heating effect due to the poor thermal conductivity of the buried SiO2 layer. We introduce aluminum nitride (AlN) thin films formed by ultra-high vacuum electron-beam evaporation with ammonia as an alternative. The chemical composition, surface morphology, and electrical properties of these films were investigated. The film synthesized at 800 °C shows a high AlN content, low surface roughness with a root-mean-square value of 0.46 nm, and high electrical resistivity. Based on thermodynamic analysis and our experimental results, the mechanism of AlN formation is proposed.

SnO2 nanowhiskers were synthesized by thermal oxidation with and without a gold film as a catalyst. The SEM images reveal wire-like and rod-shaped nanowhiskers about several hundred micrometers in length and 100 nm in diameter. The three observed Raman peaks at 474, 632, and 774 cm � 1 indicate the typical rutile phase which is in agreement with the X-ray diffraction results. The photoluminescence properties were measured at room temperature. The peaks at 342 nm corresponding to the excitation transitions from the conduction band to the valence band of the SnO2 nanowhiskers were not observed. However, a strong emission band at w600 nm was detected indicating the existence of oxygen vacancies in both samples. A new emission band at w398 nm was also observed in the sample with the gold film and it could be attributed to the near band-edge emission. 2005 Elsevier Ltd. All rights reserved.

Lead zirconium titanate (Pb(Zr0.5Ti0.5)O3, PZT) ferroelectric thin films were successfully deposited on platinum-coated silicon substrates and platinum-coated silicon substrates with a PbTiO3 interlayer by using a modified sol–gel spin-coating process, using zirconium oxynitrate dihydrate as the zirconium source. The precursor solution for spin coating was prepared from lead acetate trihydrate, zirconium oxynitrate dihydrate, and tetrabutyl titanate. The use of zirconium oxynitrate instead of the widely used zirconium alkoxide provided more stability to the PZT precursor solution and a well-crystallized structure of PZT film at a relatively low processing temperature. PZT films that were annealed at a temperature of 700°C for 2 min via a rapid thermal annealing process formed a well-crystallized perovskite phase of PZT films and also had nanoscale uniformity. The microstructure and morphology of the prepared PZT thin films were investigated via X-ray diffractometry, transmission electron microscopy, and atomic force microscopy techniques. The values for the remnant polarization (P) and coercive electric field (E) of the PZT films that were obtained from the P–E loop measurements were 3.67 μC/cm2 and 54.5 kV/cm, respectively.

The effect of the Si1−xGex source with an underlying p + region on the suppression of the floating body effects in a partially depleted silicon-on-insulator (SOI) metal oxide silicon field effect transistor (MOSFET) is numerically investigated. Compared to a conventional SOI MOSFET, the kink effect and anomalous sub-threshold slope are reduced and the breakdown voltage is substantially increased. The detailed suppression mechanism is also studied. Our results suggest that the narrow bandgap Si1−xGex source and buried p + region are favorable to

Relaxed SiGe-on-insulator (SGOI) is an attractive material to fabricate strained Si structures. Separation-by-implantation-of-oxygen (SIMOX) is a competing method to synthesize SGOI materials. In this work, pseudomorphic SiGe grown directly on Si substrate without any buffer layer SiGe/Si were implanted with 3 × 1017 cm−2 oxygen ions at 60 kV followed by thermal treatment. Our results show that the sample structure strongly depends on the thermal history. Ge diffusions mainly occur at the beginning stage of the high temperature process. Oxygen segregation and Ge diffusion during the annealing process were investigated using Rutherford backscattering spectroscopy/channeling, high-resolution X-ray diffraction, and high-resolution transmission electron microscopy. We introduce a novel two-step annealing process to reduce Ge loss during the high temperature annealing. Sharp interfaces and good crystal quality SGOI structure was obtained. Our results indicate that the SIMOX process for silicon-on-insulator (SOI) fabrication can be adopted to produce SGOI.

We have made a series of [AxB60−x]n multilayers and another series of [CxB60−x]n multilayers, where A=Fe15Ni85, B=Fe25Ni75, C=Co35Ni65, n=2 is the period, and xA (or xC) is the thickness of layer A (or layer C) in nanometer, respectively. The deposition temperature Ts was 340 °C. The magnetic properties, such as anisotropic magnetoresistance Δρ/ρo, saturation magnetostriction λs, and anisotropy field Hk, were measured. Although Δρ/ρo of the [C60]2 film is larger than that of the [B60]2 film, Hk of the former is also much larger. Therefore, the magnetoresistance (MR) sensitivity S, defined as the slope at the point of inflection of the MR curve, is not gained for either single-layered film. A similar situation exists between the [A60]2 and [B60]2 films, except Hk of the former is only slightly larger. Besides, λs 0 for Fe25Ni75 alloy (the [B60]2 film). Despite these unfavorable facts, we think that if the multi-layered [AxB60−x]n or [CxB60−x]n film could be formed, it is possible to find the optimal sample, with either the composition X A 0 or X C 0 , which exhibits good MR sensitivity S, while at the same time zero λs. Indeed, we found that: (1) when X A 0 = 50 nm , S can be as high as 1.9%/Oe, and (2) when X C 0 = 35 nm , S is 0.40%/Oe. More importantly, we have shown that Ts=340 °C is the best choice for the [A/B] multilayers, when a more precise control of xA is required in order to get the linear dependence of λs on xA.

A single-crystalline Si/SiO2/poly-WSix/Sub-Si structure has been successfully fabricated by a new method incorporating a standard smart-cut® technique and a high temperature reaction between tungsten and silicon. Annealing at 800–1100 °C does not only strengthen the bonding of the wafers but also induces solid phase reaction of deposited tungsten and silicon. A poly-crystalline WSix (1 < x < 2) layer with a tetragonal structure is formed below the buried oxide layer. Cross section images of TEM show three steep interfaces of the four layers. It is found that increasing the annealing temperature is in favour of decreasing the sheet resistance of tungsten silicide and improving the crystal quality of the top silicon layer. However, a spreading resistance profile measurement shows that annealing under high temperature (≥1000 °C) will induce diffusion of tungsten into the Si substrate which is confirmed by the EDX results and the reason is presented.

Low-temperature photoluminescence in the infrared region of hydrogen implanted single crystalline silicon is investigated. Both beam-line ion implantation and plasma immersion ion implantation (PIII) are used. The beam-line implanted samples show a broad photoluminescence band below the band gap, whereas the PIII implanted samples show at least one more peak at 1.17 eV and a much wider photoluminescence band. The origins are investigated and the peak at 1.17 eV appears to originate from nonphonon emission enhanced by lattice disorder. Our results suggest that PIII may be a better technique than beam-line ion implantation in introducing a certain disorder into the silicon lattice to circumvent the conservation of quasimomentum and consequently enhance the light emission efficiency from the modified Si samples. Our conclusion is further supported by results from plasma implanted porous Si.

A two-dimensional numerical analysis is performed to investigate the self-heating effects of metal-oxide-silicon field-effect transistors (MOSFETs) fabricated in silicon-on-aluminum nitride (SOAN) substrate. The electrical characteristics and temperature distribution are simulated and compared to those of bulk and standard silicon-on-insulator (SOI) MOSFETs. The SOAN devices are shown to have good leakage and subthreshold characteristics. Furthermore, the channel temperature and negative differential resistance are reduced during high-temperature operation, suggesting that SOAN can mitigate the self-heating penalty effectively. Our study suggests that AlN is a suitable alternative to silicon dioxide as the buried dielectric in SOI, and expands the applications of SOI to high temperature.

Metal-insulator-semiconductor (MIS) structures containing Ge nanocrystals embedded in both Al2O3 and ZrO2/Al2O3 are fabricated by an ultra-high vacuum electron-beam evaporation method. Secondary ion mass spectroscopy (SIMS) results indicate that Ge embedded in Al2O3 diffuses towards the surface of the Al2O3 layer after annealing at 800°C in N2 ambient for 30 min. Ge embedded in ZrO2/Al2O3 is stable, thus inducing less leakage current. Capacitance voltage studies indicate that annealing can effectively passivate the negatively charged trapping centers. Memory effect of the Ge nanoclusters is verified by hysteresis in the C-V curves in the Al2O3/Ge+Al2O3/Al2O3 and ZrO2/Ge+Al2O3/Al2O3 samples.

Relaxed SiGe-on-insulator (SGOI) is a suitable material to fabricate strained Si structures. Separation-by-implantation-of-oxygen (SIMOX) is a competing method to synthesize SGOI materials. In this work, SiGe/Si samples were implanted with 3×1017 cm−2 oxygen ions at 60 kV, followed by high-temperature annealing. Oxygen segregation and Ge diffusion during the annealing process were investigated using Rutherford backscattering spectroscopy/channeling (RBS/C), high-resolution x-ray diffraction (HRXRD), and high-resolution transmission electron microscopy (HRTEM). Our results show that the sample structure strongly depends on the thermal history and Ge diffuses mainly at the beginning stage of the high-temperature process. The process can be improved by introducing an annealing step at a medium temperature before high-temperature annealing, and sharper interfaces and good crystal quality can be obtained. Our results indicate that the SIMOX process for silicon-on-insulator (SOI) fabrication can be adopted to produce SGOI.

Si C films (SiC) are synthesized by methaneyacetylene plasma immersion ion implantation (PIII) into silicon using self1– xx ignited glow discharge and their properties are investigated. The synthesized SiC films have similar elemental composition (ratio) as that of the methane and acetylene precursors, except that the hydrogen content is higher for the films fabricated using methane. The films undergo a transformation from a-Si C :H to a multi-phase structure with increasing annealing temperature. The 1– xx amount of Si–C bonds increases with annealing temperature whereas that of the C–C bonds changes in an opposite manner. At high annealing temperature, graphitization takes place in the carbon clusters in the films but the extent is limited. At 1300 8C, the C–C bonds almost disappear completely. 2003 Elsevier B.V. All rights reserved.