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Two turn-key surface potential-based compact models are developed to simulate multigate transistors for integrated circuit (IC) designs. The BSIM-CMG (common-multigate) model is developed to simulate double-, triple-, and all-around-gate FinFETs and it is selected as the world's first industry-standard compact model for the FinFET. The BSIM-IMG (independent-multigate) model is developed for independent double-gate, ultrathin body (UTB) transistors, capturing the dynamic threshold voltage adjustment with back gate bias. Starting from long-channel devices, the basic models are first obtained using a Poisson-carrier transport approach. The basic models agree with the results of numerical two-dimensional device simulators. The real-device effects then augment the basic models. All the important real-device effects, such as short-channel effects (SCEs), quantum mechanical confinement effects, mobility degradation, and parasitics are included in the models. BSIM-CMG and BSIM-IMG have been validated with hardware silicon-based data from multiple technologies. The developed models also meet the stringent quality assurance tests expected of production level models.

In this paper, 2D MOSFET operation of a fully-depleted double-gate bulk MoS 2 is studied at a quasi-flatband of the back-gate for the first time. Several key device parameters such as equivalent oxide thickness (EOT), carrier concentration, flatband voltage, dielectric constant and carrier mobility were extracted from I-V and C-V characteristics and at room temperature. In a similar operation to the inversion-mode SOI MOSFETs in [1], the backgate was used to keep a sheet of mobile charges on the flake back-side by its quasi-flatband operation at a fixed voltage (0 V). Afterward, the top-gate was used as the active gate to perform mobile charge accumulation or depletion in the channel. Fig. 1 shows the device architecture together with the high frequency R-C equivalent circuit model for this underlap gate architecture. Fig. 2 represents the top-view microscope picture of the fabricated MoS 2 bulk MOSFET with a flake thickness of 38 nm, measured by AFM. The fabrication steps include mechanical exfoliation of MoS 2 crystals on a 260 nm thick oxidized Si substrate, e-beam lithography to make S/D pads, 50 nm Ni by thermal evaporation and lift-off, gate patterning, high-k/metal-gate stack deposition (1 nm of SiO x by thermal evaporation, 11 nm of ZrO 2 by ALD deposition at 105 °C, 30 nm of Ni by thermal evaporation) and lift-off. The measurements were done at room temperature using an Agilent B1500A Semiconductor Parameter Analyzer. Fig. 3 shows its I d -V g , reporting a subthreshold slope of 110 mV/dec. and I on /I off of ∼1×105, both at V ds =100 mV.

We present an efficient approach to model the effects of vertical non-uniform doping in bulk MOSFETs. The impact of vertical non-uniform doping on device characteristics is analyzed through systematic TCAD simulations. The qualitative nature of the observed effects is also confirmed by the experimental data available in the literature. A modeling methodology for these effects is developed on BSIM6 model framework. The proposed model is in good agreement with the TCAD simulations.