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7. Power-Performance Trade-Off in 7 nm Designs

Author

Chentouf, Mohamed, Cherif, Lekbir, Alaoui Ismaili, Zine El Abidine, Angrisani, Leopoldo, Series Editor, Arteaga, Marco, Series Editor, Panigrahi, Bijaya Ketan, Series Editor, Chakraborty, Samarjit, Series Editor, Chen, Jiming, Series Editor, Chen, Shanben, Series Editor, Chen, Tan Kay, Series Editor, Dillmann, Rüdiger, Series Editor, Duan, Haibin, Series Editor, Ferrari, Gianluigi, Series Editor, Ferre, Manuel, Series Editor, Hirche, Sandra, Series Editor, Jabbari, Faryar, Series Editor, Jia, Limin, Series Editor, Kacprzyk, Janusz, Series Editor, Khamis, Alaa, Series Editor, Kroeger, Torsten, Series Editor, Li, Yong, Series Editor, Liang, Qilian, Series Editor, Martín, Ferran, Series Editor, Ming, Tan Cher, Series Editor, Minker, Wolfgang, Series Editor, Misra, Pradeep, Series Editor, Möller, Sebastian, Series Editor, Mukhopadhyay, Subhas, Series Editor, Ning, Cun-Zheng, Series Editor, Nishida, Toyoaki, Series Editor, Pascucci, Federica, Series Editor, Qin, Yong, Series Editor, Seng, Gan Woon, Series Editor, Speidel, Joachim, Series Editor, Veiga, Germano, Series Editor, Wu, Haitao, Series Editor, Zhang, Junjie James, Series Editor, Hajji, Bekkay, editor, Tina, Giuseppe Marco, editor, Ghoumid, Kamal, editor, Rabhi, Abdelhamid, editor, and Mellit, Adel, editor

Published
2019
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8. ASIC Physical Design Flow: Power Saving Opportunities on Interconnection Components

Author

Cherif, Lekbir, Benallal, Jalal, Darmi, Mohammed, Chentouf, Mohamed, Elgouri, Rachid, Hmina, Nabil, Angrisani, Leopoldo, Series Editor, Arteaga, Marco, Series Editor, Panigrahi, Bijaya Ketan, Series Editor, Chakraborty, Samarjit, Series Editor, Chen, Jiming, Series Editor, Chen, Shanben, Series Editor, Chen, Tan Kay, Series Editor, Dillmann, Rüdiger, Series Editor, Duan, Haibin, Series Editor, Ferrari, Gianluigi, Series Editor, Ferre, Manuel, Series Editor, Hirche, Sandra, Series Editor, Jabbari, Faryar, Series Editor, Jia, Limin, Series Editor, Kacprzyk, Janusz, Series Editor, Khamis, Alaa, Series Editor, Kroeger, Torsten, Series Editor, Li, Yong, Series Editor, Liang, Qilian, Series Editor, Martín, Ferran, Series Editor, Ming, Tan Cher, Series Editor, Minker, Wolfgang, Series Editor, Misra, Pradeep, Series Editor, Möller, Sebastian, Series Editor, Mukhopadhyay, Subhas, Series Editor, Ning, Cun-Zheng, Series Editor, Nishida, Toyoaki, Series Editor, Pascucci, Federica, Series Editor, Qin, Yong, Series Editor, Seng, Gan Woon, Series Editor, Speidel, Joachim, Series Editor, Veiga, Germano, Series Editor, Wu, Haitao, Series Editor, Zhang, Junjie James, Series Editor, Hajji, Bekkay, editor, Tina, Giuseppe Marco, editor, Ghoumid, Kamal, editor, Rabhi, Abdelhamid, editor, and Mellit, Adel, editor

Published
2019
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9. Library Pruning for Power Saving During Timing and Electrical Design Rules Optimization

Author

Chentouf, Mohamed, Cherif, Lekbir, El Abidine Alaoui Ismaili, Zine, Kacprzyk, Janusz, Series Editor, Pal, Nikhil R., Advisory Editor, Bello Perez, Rafael, Advisory Editor, Corchado, Emilio S., Advisory Editor, Hagras, Hani, Advisory Editor, Kóczy, László T., Advisory Editor, Kreinovich, Vladik, Advisory Editor, Lin, Chin-Teng, Advisory Editor, Lu, Jie, Advisory Editor, Melin, Patricia, Advisory Editor, Nedjah, Nadia, Advisory Editor, Nguyen, Ngoc Thanh, Advisory Editor, Wang, Jun, Advisory Editor, and Ezziyyani, Mostafa, editor

Published
2019
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18. Power aware setup timing optimization in physical design of ASICs

Author

Mourssi Soukaina, Alaoui Ismaili Zine El Abidine, and Chentouf Mohamed

Subjects
010302 applied physics, Application-specific integrated circuit, Power consumption, Computer science, 020208 electrical & electronic engineering, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, General Engineering, Electronic engineering, 02 engineering and technology, Physical design, 01 natural sciences, Power added
Abstract

Setup timing optimization is a very important and challenging step of the physical design of Application Specific Integrated Circuits (ASICs). Many techniques are available to help the designer to close the design's setup timing. Although, all these techniques have the same objective, which is to resolve the existing setup timing violations, each one has a different power footprint. In this paper, we measured the impact of each optimization technique on power. We ran each optimization transform at different flow stages on a 100 industrial designs from different process technologies. We measured the ratio of Δpower/Δsetup_timing after legalization and global routing to include not only the power added directly by the setup timing optimization, but also the power induced indirectly by placement and global routing perturbation. Experimental results showed that by taking into account the impact on power consumption of each optimization technique, including placement legalization and the global routing, a power reduction of 7.3% on average could be achieved with no timing impact.

Published
2019

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