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This paper presents a chip level 9 bits Charge Folding Successive-Approximation-Register (SAR) Analog-to-Digital Converter (ADC) to be used in a CMOS image sensor for retinal prosthesis. It has a maximum single-ended input range of 1.8 V but only uses a supply voltage of 0.9 V for the entire ADC through the Charge Folding method. Therefore, the input range is no longer limited by the supply rail as in conventional SAR ADC. Moreover, the ADC is controlled by an internal delay line based Asynchronous Clock Generator which can be programmed to adjust the resolution of the ADC from 5 to 9 bits. Therefore, resolution adaptation function can be applied to improve the energy efficiency up to 15%. The test chip is implemented in 0.18 \mum CMOS process and occupies an area of 0.15 mm^2. At 0.9 V and 100 kS/s, the 9 bit s ADC consumes 1.33 \muW and achieves an energy efficiency of 51.3 fJ/conversion-step . In addition, the power consumption can be further reduced by scaling the supply voltage and sampling frequency. At 100 kS/s, this ADC is capable of converting the input signal at a rate equivalent to 30 frames/s for a pixel array up to 3200 pixels. [ABSTRACT FROM PUBLISHER]

A pseudo-digital pulsewidth modulation (P-DPWM) controlled boost direct current-direct current converter is presented in this brief. By applying low-voltage analog design techniques into the traditional digital pulsewidth modulation (DPWM) structure, the proposed P-DPWM achieves new features of high resolution, low power, and small area while retaining the low-supply feature of the DPWM. A test chip has been designed and fabricated in a 65-nm CMOS process with an area of 1.44 \mm^2 to validate its performance. A peak efficiency of 86% is achieved. The correct functionality is also demonstrated with the controller supply as low as 0.42 V, which is ideal for sub-1 V low-supply applications. [ABSTRACT FROM PUBLISHER]

This paper aims to develop a novel adaptive gate switching controller (AGSC) for discontinuous conduction mode (DCM) dc–dc converters, in an attempt to reduce the power losses caused by nonideal gate switching operations. The proposed AGSC employs a dead-time controller (DTC) and a zero-current detector (ZCD) to turn ON and OFF the synchronous switch, respectively. Both the DTC and the ZCD perform self-calibration according to the converter switching node voltage, allowing the AGSC achieves near-optimal gate switching control regardless of the operating frequency, process variation, power device variation, as well as source voltage and load current variation. The proposed AGSC can have useful applications in many DCM dc–dc converters, e.g., buck, boost, and buck–boost converters. For a proof of concept, in this paper, a boost converter was implemented with the proposed AGSC in a 0.18-μm 3.3-V CMOS process with an area of 1.5 mm^2. The experimental results demonstrate precise control of the gate switching operations, and the boost converter at 1.2-V/2.5-V nominal input/output achieves a peak efficiency of 86% at 30-mA load current. [ABSTRACT FROM AUTHOR]

This paper presents a chip level 9 bits Charge Folding Successive-Approximation-Register (SAR) Analog-to-Digital Converter (ADC) to be used in a CMOS image sensor for retinal prosthesis. It has a maximum single-ended input range of 1.8 V but only uses a supply voltage of 0.9 V for the entire ADC through the Charge Folding method. Therefore, the input range is no longer limited by the supply rail as in conventional SAR ADC. Moreover, the ADC is controlled by an internal delay line based Asynchronous Clock Generator which can be programmed to adjust the resolution of the ADC from 5 to 9 bits. Therefore, resolution adaptation function can be applied to improve the energy efficiency up to 15%. The test chip is implemented in 0.18 μm CMOS process and occupies an area of 0.15 mm(2). At 0.9 V and 100 kS/s, the 9 bit s ADC consumes 1.33 μW and achieves an energy efficiency of 51.3 fJ/conversion-step . In addition, the power consumption can be further reduced by scaling the supply voltage and sampling frequency. At 100 kS/s, this ADC is capable of converting the input signal at a rate equivalent to 30 frames/s for a pixel array up to 3200 pixels.