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Unprecedented computing power is pursued for the next generation of big data, cloud computing and artificial intelligence, and it is driving all kinds of new technology in semiconductor industry now. Integrated fan-out on substrate (InFO_oS) packaging technology emerges as one of the innovative package solutions to connect multiple dies, and therefore could deliver higher performance than conventional one-die package. Due to extremely high power is accommodated in one single package, accurate thermal analysis of it is crucial to avoid thermal issue of integrated chips.In order to understand the thermal characteristic of integrated fan-out on substrate package, not only a detailed package thermal model was constructed but also a thermal test vehicle (TTV) was developed in this work. Standard JEDEC package thermal resistance of junction-to-case experiments was conducted with large body InFO_oS TTV, including multiple heat sources. It is shown that the thermal model can achieve great accuracy compared with measurement result. Meanwhile, as thermal interface material (TIM) between die and metal lid plays a big role of thermal resistance of junction-to-case, different kinds of TIM materials were adopted in this TTV to characterize their thermal performance. The effect of bond line thickness (BLT) of TIM was also investigated as it is another key factor.In this study, a detail InFO_oS thermal model was verified and fundamental thermal characteristic of it was completed. Furthermore, based on the correlated thermal model, a series of thermal simulation was executed to study thermal power budget with advanced thermal solutions and with different TIM materials adopted in InFO_oS package. It would be practical and beneficial to implement this methodology in design phase to reduce thermal risk in system application of end product.

When power consumption in smartphones becomes much higher, several significant impacts occur due to its small form factor, such as performance degradation and worse user experience. Thus, power estimation/mapping is essential and useful for dynamic power management and power model validation for smartphones. In this work, first, we build the power-to-temperature (P-to-T) equations for thermal sensors from the existing system-level thermal model and calibrate them using the least squares fitting. Furthermore, we develop an efficient method for the temperature-to-power (T-to-P) mapping, which obtains the power consumption of components by utilizing temperatures of thermal sensors. Experiments show that this work can estimate power profile efficiently for both steady-state and transient results.

As the race of CMOS technology continues, process node has shrunken from micrometer to 7 nanometer nowadays. One of the advantages with the advanced process node is that lower operating voltage comes with it and therefore the dynamic power has been lowered down significantly. But unfortunately, leakage power has emerged as another critical concern especially for thermal runaway issue. Thermal resistor-capacitor model is one of the mainstream dynamic compact thermal models for transient thermal analysis. Since leakage power is strongly temperature-dependent, in order to conduct transient thermal simulation more accurately, leakage effect must be considered. In this paper, we proposed a methodology of leakage-aware dynamic compact thermal modeling which integrates thermal resistor-capacitor model with a temperature-dependent leakage model. To prove the validity of proposed model, a customized testing program was developed to create artificial leakage effect on thermal test. The validation result shows that the proposed model can not only reflect the leakage impact on IC's transient thermal behavior properly but also keep the average error of junction temperature less than 6%. In the case study, a systematic investigation on thermal runaway was explored, the leakage boundary of corner IC could be identified to avoid thermal runaway problem.

This work presents a system-level thermal simulator, Phone-nomenon, to predict the thermal behavior of smartphone. First, we study the nonlinearity of internal and external heat transfer mechanisms and propose a compact thermal model. After that, we develop an iterative framework to handle the nonlinearity. Compared with a commercial tool, ANSYS Icepak, Phonenomenon can achieve two and three orders of magnitude speedup with 3.58% maximum error and 1.72°C difference for steady-state and transient-state simulations, respectively. Meanwhile, Phone-nomenon also fits the measured data of a built thermal test vehicle pretty well.

In conventional smartphone system thermal analysis, system on chip (SoC) was deemed as one single heat source which was an effective way to identify integrated circuit (IC) and skin thermal problem. However, as the heterogeneous computing architecture is getting much more powerful and complex, a sophisticated thermal model of CPU and GPU is required to conduct thermal analysis with their individual and coupling thermal effects. To this end, an innovative dynamic compact thermal model (DCTM) was proposed to enable performance and power optimization under thermal limit. The proposed DCTM could capture their thermal coupling effect and still keep the simplicity of model structure like conventional RC ladder model. Meanwhile, the transient behavior of peripheral ICs, such as power management IC, was also included and could be analyzed simultaneously. To prove the validity of proposed DCTM, a series of experiments was conducted with thermal test vehicle in a real phone enclosure, including multiple-heat-sources SoC and peripheral IC. The validation results showed that it could capture the thermal characteristic of SoC and the peripheral IC in smartphone system with maximum root mean square error less than 1.58°C for all test cases. Moreover, a power budget allocation case study was explored, and the result showed that 8% extra power budget could be obtained if a well allocation strategy is decided.

To sustain Moore’s law, three-dimensional integrated circuit (3-D IC) is a promising solution to achieve high performance and low cost targets. However, its operating temperature is higher than that of a 2-D IC because of its high power density of stacked dies and ill of heat dissipation capability. Therefore, on-chip thermal effects have become major concerns of 3-D ICs. Utilizing look-up table approach, this paper, LUTSim, provides two thermal simulation engines, I-LUTSim and S-LUTSim, to efficiently calculate the thermal profile of a 3-D IC. I-LUTSim is suitable for full-chip thermal analysis, and S-LUTSim is suited for incremental-thermal updating. With utilizing the prebuilt tables, compared with a commercial tool ANSYS, the absolute error of I-LUTSim is less than 0.29%. Moreover, with negligible loss of accuracy, I-LUTSim can be 38.8 times faster than a well-known matrix solver SuperLU for performing full-chip thermal simulation. Besides, S-LUTSim can be over 1.05 million times faster than SuperLU for adjusting the thermal profile after inserting/removing a through silicon via.

Package-on-package (PoP) has become a popular package for high performance SoC in mobile world in recent years as it occupies less area on printed circuit board by stacking DRAM on top of the package of SoC. However, this 3D package makes the thermal coupling effect between SoC and DRAM more prominent. Hence, a sophisticated thermal analysis including transient behavior would be beneficial to avoid unexpected performance suffering from throttling and maximize the power budgeting for SoC and DRAM.

Fluoxetine (FT), fluvoxamine (FX), sertraline (ST) and trazodone (TD) are new type of antidepressants acting as selective serotonin reuptake inhibitors (SSRIs). In structures, they all have chromophore and can be easily monitored by UV absorption spectrophotometry. A simple isocratic high-performance liquid chromatographic method with ultraviolet detection (215 nm) was developed for the simultaneous quantification of FT, FX, ST and TD. The determination range of the method is over 10.0–400.0 μM for each drug. The detection limits (S/N = 3, injection 20 μL) are about 0.1 μM for TD, 0.2 μM for FT, FX and ST. The relative standard deviation and relative error of the method for intra- and inter-day analyses of FT, FX, ST and TD were all below 3.7%. Application of the method to the analysis of FT, FX or ST in pharmaceutical product proved feasible. The method could be used for the quality control assay of the analytes in bulk and in formulations.

This work presents an iterative look-up table based thermal simulator, I-LUTSim, to efficiently estimate the temperature profile of three-dimensional integrated circuits. I-LUTSim includes two stages. First, the pre-process stage constructs thermal impulse response tables. Then, the simulation stage iteratively calculates the temperature profile via the table lookup. With this two-stage scheme, the maximum absolute error of I-LUTSim is less than 0.41% compared with that of a commercial tool ANSYS. Moreover, I-LUTSim is at least an order of magnitude faster than a fast matrix solver SuperLU [1] for the full-chip temperature simulation.

This work introduces the concept of thermal yield profile for the hot-spot identification with considering process variations and provides an efficient estimating technique for the thermal yield profile. After executing a mixed-mesh strategy for generating statistical polynomial expression of the on-chip temperature distribution, the thermal yield profile is obtained by a skew-normal based moment matching technique. Comparing with the Monte Carlo method, experimental results demonstrate that our method can efficiently and accurately estimate the thermal yield profile. With the same level of accuracy, our skew-normal based method achieves 215x speedup over the state of the art, APEX [1], for estimating the thermal yield profile. Moreover, results show that our mixed-mesh statistical polynomial expression generator achieves 130x speedup over the statistical collocation based method [2] and still accurately estimates the thermal yield profile.

Redundant via insertion is a useful technique to alleviate the yield loss and elevate the reliability of VLSI designs. While extra vias are inserted into the design, the electronic properties of designed circuit might be altered, and the circuit timing might be changed and needs to be efficiently re-analyzed. Therefore, a fast timing (incremental timing) analyzer is required to assistant the redundant via insertion procedure. This work develops an efficient redundant via insertion method under timing constraints. Firstly, an effectively incremental circuit timing analysis method is developed, and the redundant via insertion task is transformed into a mixed bipartite-conflict graph matching problem. Then, the insertion problem is solved by a timing-driven minimum weighted matching algorithm. The experimental results show that the developed algorithm can achieve 3.2% extra insertion rates over the method without considering timing effects, which all redundant vias would be removed if the timing of that net does not meet the timing requirements, in average. In addition, the developed incremental timing analysis mechanism can speed up the runtime of redundant via insertion procedure under timing constraints by over 34 times in average.

With the advance of nanometer technologies, the process variations play important roles in integrated circuit designs. The conventional corner value timing analysis becomes less effective and grossly conservative. Given a limited amount of measurement silicon data and without any distribution assumptions, this work develops a spatial correlation estimation methodology with the bootstrap resampling technique to improve the extraction correctness of the spatial correlation. By constructing the confidence interval of the spatial correlation, the correlation between two path delays can be got, and the high coverage rate for the true spatial path delay correlation has been demonstrated from the experimental results.

A simple and sensitive liquid chromatographic method is described for the analysis of amantadine and memantine. The method is based on the derivatization of amantadine and memantine extracted from alkalified samples with (2-naphthoxy)acetyl chloride at mild conditions. The resulting derivatives were analyzed by isocratic HPLC with a fluorimetric detector (lambdaex, 227 nm; lambdaem, 348 nm). The linear range for the determination of amantadine or memantine spiked in urine (1.0 ml) was 1.0-10.0 nmol with a detection limit of about 0.2 nmol (S/N = 3; injected sample 20 microl). Only amantadine preparations are available on our local market, and application of the method to the analysis of amantadine in formulation and in the urine of a dosed subject was demonstrated and proved feasible. Quantitation of AT in tablets or capsules is capable in the linear range of 2.0-50.0 microM. Toluene was used as the solvent for extracting amantadine or memantine in samples and the resulting toluene extract was directly subjected to subsequent derivatization without solvent replacement leading to a simpler analytical procedure.

When Fe3Sn powders were milled for 30 h, the X-ray diffraction pattern of the as-milled powders revealed a broad peak typical for an amorphous phase. Nanocrystals appeared after 30-h milling for Al-doped Fe3Sn powders and the amount of nanocrystals increased with the increase of the amount of aluminum doped. Owing to the formation of nanocrystals, the saturation magnetization of the as-milled powders increased with Al doping. However, the coercivity exhibited an opposite tendency compared with the saturation magnetization. The crystalline phases were obtained by annealing as-milled powders at 800°C for 0.5–5 h. The crystalline Fe3Sn phase was formed for an Al (3.63 wt%)–Fe3Sn sample after 0.5-h annealing with a saturation magnetization of 105 emu/g.

The coercivity of the as-milled samples had a maximum value of 90 Oe for 33.9 wt%Zn. When annealed at 400° C for 10 days, the metastableεphase, and Γ and Γ1phases appeared with 9.75 wt%Zn, and 33.7 wt%Zn, respectively. The α-Fe phase disappeared at 73.3 wt%Zn, causing the saturation magnetization to decrease drastically to 2 emu/g. The precipitation of the metastableεphase in the annealed samples containing 24.2 wt%Zn had a maximum coercivity of 175 Oe. A single α-Fe phase is obtained upon solution treatment at 800° C for 1 h. After aging, precipitation of theεphase occurred for Zn content above 6.74 wt%. The saturation magnetisation and the coercivity of aged samples were larger than those of solution-treated samples.