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The charge trapping characteristics of HfO2 dielectric under the electrostatic discharge (ESD) high-field current impulses were studied. It is found that the charge trapping phenomenon is different from that of the conventional dc stress. The results show the interface-trapped charges are built at the low stress regime, but the positive oxide-trapped charges are rapidly built up while increasing the stress voltage, which eventually dominates the oxide breakdown. The origin of the positive oxide-trapped charges at the medium stress regime is most likely the hole trapping. At high stress regime, the main contribution of the positive oxide-trapped charges results from the electric-field enhanced defect generation. Using the Fowler derivative method, the degradation characteristics of HfO2 oxides under the ESD stress are investigated. Compared with SiO2, the severer ESD-induced charge trapping in HfO2 dielectric is observed which can be elucidated by the inherent bonding nature of metal oxide. [ABSTRACT FROM AUTHOR]

Metal-oxide-semiconductor capacitors with Pr2O3/oxynitride laminated gate dielectrics were fabricated. The current transportation of Al/Pr2O3/SiON/n-Si devices was studied at temperatures ranging from 300 to 400 K. The dominant conduction mechanism at low electric field (<0.6 MV/cm) is the hopping conduction in the laminated gate dielectrics. The determined hopping distance and activation energy is about 1.5 nm and 50±1 meV, respectively. However, the dominant conduction mechanism at high electric field (>2 MV/cm) is the Poole–Frenkel emission in which the trap energy level determined from Arrhenius plot is about 0.56±0.01 eV. [ABSTRACT FROM AUTHOR]

Metal-oxide-semiconductor capacitors incorporating Dy2O3 dielectric were fabricated and investigated. In this work, the electrical conduction mechanisms of 12 nm Dy2O3 thin films as functions of temperature were studied. The dominant conduction mechanisms of the Al/Dy2O3/p-Si metal-dysprosium oxide-semiconductor capacitor are the space-charge-limited current from 350 to 525 K and the Schottky emission from 300 to 325 K in the accumulation mode. Three different regions were observed in the current-density–voltage (J-V) characteristics at 350 K, namely, Ohm’s law region, trap-filled-limited region, and Child’s law region. The activation energy in Ohm’s law region calculated from the Arrhenius plots is about 0.2 eV. This energy is attributed to shallow traps, distributed near the conduction band edge in the forbidden gap. The trap capture cross section is about 3.2×10-21 cm2. The electronic mobility, trap density, dielectric relaxation time, and density of states in conduction band were obtained from the space-charge-limited conduction at 350 K. [ABSTRACT FROM AUTHOR]

Metal-oxide-semiconductor capacitors incorporating HfO2 dielectrics were fabricated and investigated. In this work, the structural and electrical characterizations were performed at the interfaces of HfO2/Si and Al/HfO2, respectively. The physical analyses reveal that an interfacial layer of Hf-silicate between 700 °C-annealed HfO2 and Si was formed. The dominant conduction mechanisms of the Al/HfO2/p-Si structure are the Schottky emission at high temperatures (>=465 K) and low electric fields (<=2.2 MV/cm) and the Fowler-Nordheim tunneling at low temperature (77 K) and high electric fields (>=2.6 MV/cm), respectively. The electron effective mass in HfO2 and the barrier height at the Al/HfO2 interface are evaluated using both the intercept of the Schottky plot and the slope of the Fowler-Nordheim plot. Therefore, the barrier height at the Al/HfO2 interface was determined to be about 0.94 eV. The electron effective masses in HfO2 are 0.4m0 and 0.09m0 for the effective oxide thickness (EOT)=6 nm and EOT=3.15 nm, respectively. [ABSTRACT FROM AUTHOR]

Metal-oxide-semiconductor capacitors that incorporate ZrO2 gate dielectrics were fabricated by radio frequency magnetron sputtering. In this work, the essential structures and electrical properties of ZrO2 thin films were investigated. C-V, energy dispersive x-ray spectrometry, and transmission electron microscopy analyses reveal that an interfacial layer was formed, subsequently reducing the k value of the annealed ZrO2 thin films. Additionally, the mechanisms of conduction of the Al/ZrO2/p-Si metal/zirconium oxide/semiconductor structure were studied with reference to plots of standard Schottky emission, modified Schottky emission, and Poole–Frenkel emission. According to those results, the dominant mechanisms at high temperatures (>425 K) are Poole–Frenkel emission and Schottky emission in low electric fields (<0.6 MV/cm) and high electric fields (>1 MV/cm), respectively. Experimental results indicate that the Al/ZrO2 barrier height is 0.92 eV and the extracted trap level is about 1.1 eV from the conduction band of ZrO2. The modified Schottky emission can be applied in an electric field to ensure that the electronic mean free path of the insulator is less than its thickness. According to the modified Schottky emission model, the extracted electronic mobility of ZrO2 thin films is around 13 cm2/V s at 475 K. The mean free path of transported electrons in ZrO2 thin films is between 16.2 and 17.4 nm at high temperatures (425–∼475 K). [ABSTRACT FROM AUTHOR]

Tantalum oxide (Ta[sub 2]O[sub 5]) is an important material for future dynamic random access memory application owing to its high dielectric constant. This work examines the structural and electrical properties of Ta[sub 2]O[sub 5] thin films deposited by plasma-enhanced chemical vapor deposition using a penta ethoxy tantalum Ta(OC[sub 2]H[sub 5])[sub 5] liquid source. The x-ray diffraction pattems indicate that the as-deposited thin films are amorphous and become polycrystalline after rapid thermal annealing above 650 °C. The level of carbon contamination is below that which can be detected by Auger electron spectroscopy measurement. Electrical measurements performed on amorphous Ta[sub 2]O[sub 5] using a Au/Ta[sub 2]O[sub 5]/Pt/Ti/Si metal-tantalum oxide-metal strucmre exhibit a low leakage current, reasonable breakdown field (5.4 MV/cm), and high dielectric constant (23–25). The leakage current is 2 x 10[sup -8] A/cm[sup 2] at 1 MV/cm. In addition, the leakage current mechanism of amorphous Ta[sub 2]O[sub 5] capacitors is investigated by plotting the ln(J) vs E [sup 1/2] curves at a low electric field (<2 MV/cm) and plotting ln(J/E) vs E[sup 1/2] curves at a high electric field (>2 MV/cm). The dominant conduction mechanism is due to Schottky emission at low electrical field and Poole-Frenkel emission at high electrical field. According to our results, the Ta[sub 2]O[sub 5] thin films annealed in N[sub 2] or O[sub 2] at 800 °C exhibit a much higher leakage current than amorphous Ta[sub 2]O[sub 5] , possibly due to the out-diffusion of Ti during high temperature annealing. © 1997 American Institute of Physics. [ABSTRACT FROM AUTHOR]

Transmission line pulse measurements were used to investigate the reliability of the HfO2 dielectric under an electrostatic discharge event. Time-dependent dielectric breakdown of the gate oxide was characterized down to the microsecond time regime. The positive oxide-trapped charges Qot+ were observed beyond a certain electric field and the corresponding centroid evolution was examined. In the high-field stress regime, the field acceleration parameter of the HfO2 dielectric is smaller than that of the silicon oxynitride. We also demonstrated this phenomenon can be attributed to the stronger phonon-assisted tunneling process in the high-k dielectrics. [ABSTRACT FROM AUTHOR]

This paper develops optimization between electrostatic discharge (ESD) and latchup characteristics for a silicon-controlled rectifier (SCR)-incorporated Bipolar Junction Transistor (BJT) in a 0.18- \mu \textm , 3.3 V process. This device is composed of a floating pMOSFET embedded in a parasitic n-well/p-sub/n+ region BJT structure. The floating pMOS gate is further coupled with an RC network for controlling its switching. The floating pMOS could increase the effective width of its floating p+ region to enhance ESD robustness during ESD zapping events, whereas maintain its floating p+ region narrower during IC operation situation. With the optimized structure dimensions, this device can reach transmission-line pulse second breakdown current 6 A, ESD/ human-body model over 8 kV, which are the same as those of an SCR, and its latchup trigger current is at least 1.9 times greater. [ABSTRACT FROM PUBLISHER]