123 results on '"Chong, Kwen-Siong"'
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2. Design and Implementation of a High-Speed Low-Power K-Nearest-Neighbor-Based Algorithm for Detecting Micro-Single-Event Latchups
3. A Data Pre-Processing Module for Improved-Accuracy Machine-Learning-based Micro-Single-Event-Latchup Detection
4. Improving FPGA-based Async-logic AES Accelerator with the Integration of Sync-logic Block RAMs
5. Incremental Linear Regression Attack
6. Design and Analysis of Area and Energy Efficient Reconfigurable Cryptographic Accelerator for Securing IoT Devices
7. A High-Accuracy and Energy-Efficient CORDIC Based Izhikevich Neuron With Error Suppression and Compensation
8. A Highly Secure FPGA-Based Dual-Hiding Asynchronous-Logic AES Accelerator Against Side-Channel Attacks
9. Low Power Asynchronous Circuit Design: An FFT/IFFT Processor
10. An Asynchronous-Logic Masked Advanced Encryption Standard (AES) Accelerator and its Side-Channel Attack Evaluations
11. Non-profiling based Correlation Optimization Deep Learning Analysis
12. Ultra-Low Power Read-Decoupled SRAMs with Ultra-Low Write-Bitline Voltage Swing
13. An Energy-Efficient Deep Belief Network Processor Based on Heterogeneous Multi-Core Architecture With Transposable Memory and On-Chip Learning
14. A High-Accuracy and Energy-Efficient CORDIC based Izhikevich Neuron
15. A Power-Aware Toggling-Frequency Actuator in Data-Toggling SRAM for Secure Data Protection
16. Dual-Hiding Side-Channel-Attack Resistant FPGA-Based Asynchronous-Logic AES: Design, Countermeasures and Evaluation
17. Normalized Differential Power Analysis - for Ghost Peaks Mitigation
18. A low-voltage micropower asynchronous multiplier with shift-add multiplication approach
19. A Novel Normalized Variance-Based Differential Power Analysis Against Masking Countermeasures
20. A 16-channel low-power nonuniform spaced filter bank core for digital hearing aids
21. High Efficiency Early-Complete Brute Force Elimination Method for Security Analysis of Camouflage IC
22. An Energy-efficient Multi-core Restricted Boltzmann Machine Processor with On-chip Bio-plausible Learning and Reconfigurable Sparsity
23. High Throughput and Secure Authentication-Encryption on Asynchronous Multicore Processor for Edge Computing IoT Applications
24. A Secure Data-Toggling SRAM for Confidential Data Protection
25. A Highly Efficient Power Model for Correlation Power Analysis (CPA) of Pipelined Advanced Encryption Standard (AES)
26. A DPA-Resistant Asynchronous-Logic NoC Router with Dual-Supply-Voltage-Scaling for Multicore Cryptographic Applications
27. Radiation-Hardened-by-Design (RHBD) Digital Design Approaches: A Case Study on an 8051 Microcontroller
28. Side-Channel-Attack Resistant Dual-Rail Asynchronous-Logic AES Accelerator Based on Standard Library Cells
29. A Secure Data-Toggling SRAM for Confidential Data Protection
30. Reconfigurable Routing Paths As Noise Generators Using NoC Platform for Hardware Security Applications
31. A Highly Efficient Side Channel Attack with Profiling through Relevance-Learning on Physical Leakage Information
32. A High Throughput and Secure Authentication-Encryption AES-CCM Algorithm on Asynchronous Multicore Processor
33. Radiation Hardening By Design Integrated Circuits Enabling Low-Cost Satellites for Internet-of-Things
34. Single-Event-Transient Resilient Memory for DSP in Space Applications
35. A Comparative Analysis of 65nm CMOS SRAM and Commercial SRAMs in Security Vulnerability Evaluation
36. Asynchronous-Logic QDI Quad-Rail Sense-Amplifier Half-Buffer Approach for NoC Router Design
37. A Highly-Secured Arithmetic Hiding cum Look-Up Table (AHLUT) based S-Box for AES-128 Implementation
38. DPA-resistant QDI dual-rail AES S-Box based on power-balanced weak-conditioned half-buffer
39. Highly secured state-shift local clock circuit to countermeasure against side channel attack
40. Security analysis of asynchronous-logic QDI cell approach for differential power analysis attack
41. Highly secured arithmetic hiding based S-Box on AES-128 implementation
42. Success rate model for fully AES-128 in correlation power analysis
43. Interceptive side channel attack on AES-128 wireless communications for IoT applications
44. A single-VDD half-clock-tolerant fine-grained dynamic voltage scaling pipeline
45. Secured Low Power Overhead Compensator Look-Up-Table (LUT) Substitution Box (S-Box) Architecture
46. High performance low overhead template-based Cell-Interleave Pipeline (TCIP) for asynchronous-logic QDI circuits
47. Total Ionizing Dose (TID) effects on finger transistors in a 65nm CMOS process
48. Area-efficient and low stand-by power 1k-byte transmission-gate-based non-imprinting high-speed erase (TNIHE) SRAM
49. Experimental investigation into radiation-hardening-by-design (RHBD) flip-flop designs in a 65nm CMOS process
50. High Secured Low Power Multiplexer-LUT Based AES S-Box Implementation
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