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Process-induced variability has become a predominant limiter of performance and yield of IC products especially in a deep submicron technology. However, it is difficult to accurately model systematic process variability due to the complicated and interrelated nature of physical mechanisms of variation. In this paper, a simple and practical method is presented to decompose process variability using statistics of the measurements from manufacturing inline test structures without assuming any underlying model for process variation. The decomposition method utilizes a variant of principal component analysis and is able to reveal systematic variation signatures existing on a die-to-die and wafer-to-wafer scale individually. Experimental results show that the most dominant die-to-die variation and wafer-to-wafer variation represent 31% and 25% of the total variance of a large set of manufacturing inline parameters in 65-nm SOI CMOS technology. The process variation in RF circuit performance is also analyzed and shown to contain 66% of process variation obtained with manufacturing inline parameters.

We present a camera system for instantaneous, non-destructive capture of spectral signatures for forensic analysis. Our system detects highly probative samples in the forensic scene mixed by the multiple target objects by combining a coded aperture snapshot spectral imager with a multi-spectral detection algorithm. An Adaptive Cosine Estimator (ACE) is used to quantitatively detect and classify the probative samples from the decoded spectral datacube. In this paper, we demonstrate selected results using our system for luminescence characteristics and spectral classification of a number of samples.

This letter presents symmetric vertical parallel plate (VPP) capacitors in 65-nm silicon-on-insulator CMOS technology. Three VPP capacitors with different metal layer options are examined with respect to effective capacitance density and -factor. An effective capacitance of 2.18 and a -factor of 23.2 at 1 GHz are obtained from a 1x + 2x (M1-M6) metal layer configuration's pre-de-embedding measurement. VPP capacitor symmetry, mismatch, leakage current density, vertical scalability, and variation characteristics from a 300-mm wafer are discussed.

This letter reports the statistical analysis of circuit-level FET high-speed performance in 65-nm silicon-on-insulator CMOS technology. Practical performance metrics are derived from full 300-mm wafer measurements. The proposed circuit-level layout wiring parasitics-aware FET reflects realistic FET that is placed in circuits. Its measurement and model are directly applicable to circuit design in conjunction with multiple layers of yield and manufacturability considerations. A stretched gate-pitch NFET design shows an average current gain cutoff frequency fT of 250 GHz, with 7.6% standard deviation, 6.7% mismatch standard deviation, and maximum fT of 307 GHz. The proposed characterization methodology will become more relevant to technologies beyond 65 nm.

Coded aperture snapshot imaging (CASSI) is used for spectral classification in a compact form. A CASSI data cube is classified by using an adaptive cosine estimator (ACE), to detect target pixels, and signal-to-noise ratio (SNR) of the data cube is improved by video stabilization (VS) technique.

CMOS VCOs have been implemented for mm-wave applications [1–7], however, as the required channel bandwidth for these applications increases, wide-range VCO tuning is becoming more challenging. Even without taking into account the process variability in nanometer CMOS, a single VCO hardly achieves requirements for a mm-wave band and phase-noise performance, and it suffers from the steep VCO loop gain. Taking advantage of parallelism, using an array of VCOs is emerging as an alternative technique to implement a wide-band VCO (Fig. 16.3.1). While nanometer CMOS technology is becoming the next generation RF and mm-wave platform (because of high-speed performance due to technology scaling and and SoC integration capability), costly technology developments and mask sets further promote the use of array-based VCOs to expedite yield learning and circuit-development cycle. However, a VCO array requires more circuit area. Conventional designs are not scalable because of their size, cost, and complications for signal delivery. Technology scaling for mm-wave SoC is driven by the high-speed device performance while digital systems benefit from increased device density. In mm-wave applications, passive components, especially inductors, are responsible for area budget, since their area is not scaled with the technology. Taking advantage of nanometer FETs, the presented complementary LC-VCO is attractive for VCO arrays. It uses an LC-tank and its area is minimal and highly scalable. The use of state-of-the-art nanometer CMOS technology is essential to retain high-speed design margin for mm-wave circuits and provisions are required to make the complementary LC-VCO more scalable and manufacturable against the process variability and technology uncertainty. After all, the VCO array provides mm-wave-component performance-variability metrics as a feedback to the technology foundry. Such components are difficult and expensive to characterize and the required on-chip probe pads waste silicon area.

The paper presents a logic interconnect device (LID) to model digital circuit with near back-end-of-line (BEOL) effect, and to measure system performance. It is driven by a product inverter-based logic circuit, and it is loaded with near-BEOL wiring. The LID ring oscillator is measured and analyzed in 65nm SOI CMOS. The methodology offers in-situ characterization of near-BEOL interconnect parasitics, and dielectric constant in product circuits. It captures front-end-of-line (FEOL) and near- BEOL interactions, distinguished in deeply scaled CMOS.

This paper introduces a process variability model to determine the performance and yield of the cell broadband engine (CBE) in 65 nm SOI CMOS. The model incorporates spatial (die-to-die), temporal (manufacturing process drift), and parametric dimensions, and provides microprocessor performance tracking and comprehensive view on the process variability with embedded ring oscillator measurement at the wafer level. It extracts CBE performance regularity within die for the circuit design and models, and reveals the semiconductor manufacturing signatures in wafers and lots for process technology. The model reduces performance estimation testing requirements by surpassing conventional methodspsila accuracy by 28%.

A 5-stage CML prescaler operating up to 84 GHz is presented. The prescaler requirements, design considerations, simulations, and performance measurements are presented. The first divide-by-2 stage consumes 17.7mW at 1.8V, or 26.40 power-delay product per gate. The prescaler's phase noise gain degeneration at the sensitivity curve boundary is reported for the first time.

This paper presents a practical method to estimate IC product performance and parametric yield solely from a well-chosen set of existing electrical measurements intended for technology monitoring at an early stage of manufacturing. We demonstrate that the components of mmWave PLL and product-like logic performance in a 65 nm SOI CMOS technology are predicted within a 5% RMS error relative to mean.

A wideband millimeter-wave (mmWave) CML static divider fabricated in 65 nm SOI CMOS technology is presented. The mmWave system realization trend and engagement in sub-100 nm CMOS technologies are summarized. CML static dividerpsilas circuit analysis, sensitivity curve, and simulations are explored. The input-locking hysteresis and divider DC bias tuning are employed to extend the divider operation range. The divider performance measurements are presented with hysteresis-assisted gain and figure-of-merits. A scalable statistical estimation is proposed, and it is validated with a full 300 mm wafer measurements. The divider exhibits wideband mmWave performance to overcome the process variability in sub-100 nm CMOS processes.

The process variability of a V-band LC-VCO implemented in 65 nm SOI CMOS is examined. A complementary LC-VCO design, test set up, and measurements are presented. One lot of 300 mm wafers are measured for statistics. There are 8 wafers in the lot, and 67 VCOs per wafer. The VCO frequency tuning range statistics, analog variability against digital benchmark, yield estimation, and intra- vs. inter-wafer variations are analyzed and discussed. The VCO average frequency tuning is 63.7-69.6 GHz, and it shows 90% yield from 65.1 to 67.9 GHz.

A CML static divider operates up to 82.4 GHz with 90% yield for 0 dBm input is statistically measured and estimated. The proposed method of statistical measurement enables reliable sensitivity curve estimation by 55% of standard variation, based on the analytic model, simulations, and scalable DC and RF measurements for the first time. A 300 mm full wafer is scanned for the validation.

An RF and mm-wave platform developed in 65 nm SOI CMOS technology is presented. The SOI FET performance in a wired cell is measured up to fT=300 GHz and 200 GHz for NFET and PFET. Ring oscillator records 3.6 psec minimum inverter stage delay. Back-end-of-line vertical native capacitor (VNCAP) and on-chip inductor performances are reported. The performance scaling trends of mmWave PLL front-end components are presented.

The GHz-digital clock jitter measurement capabilities in time and frequency domains are explored. A 101-stage inverter-based ring oscillator implemented in 65 nm SOI is used as a clock source. Both domains produce clock period jitters reliably. Cycle-to-cycle jitters are obtained in time, and confirmed In frequency domain. Time interval error jitters are calculated from phase noise, and time-domain results are matched with frequency-dependent jitters. The convergence and limitations of time and frequency-domain jitter measurements are presented.

A 2:1 static frequency divider using a bandpass load was fabricated in a digital 90 nm SOI CMOS technology. The divider exhibits a maximum operating frequency of 81 GHz at 1.2 V, and a core power of 15.6 mW. The divider can operate down to 0.5 V at a maximum operating frequency of 75.6 GHz with a core power of 2.75 mW.

We present record-performance RF devices and circuits for an SOI CMOS technology, at 35 nm Lpoly. Critical RF/analog figure of merits in FET such as current gain cut-off frequency (fT), 1/f noise, and high-frequency noise figure at various bias and temperature conditions are measured and modeled to enable high-performance circuit design. Measurement results show peak fT's of 340 GHz and 240 GHz for 35 nm Lpoly NFET and PFET, respectively. At sub-35 nm Lpoly, 360 GHz fT NFET and 260 GHz fT PFET are demonstrated. High-Q, high-density vertical native capacitors (VNCAPs) and on-chip inductors are integrated. RF-operable ring oscillator (RFRO) demonstrates a 3.58 psec delay and a SSB phase noise of -107 dBc/Hz at 1 MHz offset. LC-tank VCO operates at 70 GHz with 9.5% tuning range. The maximum operating frequency of a static CML divider is 93 GHz while dissipating 52.4 mW.

A combination of LC-VCO and 2:1 CML static frequency divider has been fabricated in 65 nm SOI CMOS technology and operates at 70 GHz. A cascoded buffer amplifier is used in VCO-to-divider connection to compensate for the power losses caused by interconnect parasitics, and inductive peaking is employed for bandwidth enhancement. The bias condition of the frequency divider has been tuned to find an optimal bias point in existence of VCO and frequency divider operating range variation. The inter-die variation of VCO and divider performance variations over a wafer and their correlation have been estimated.

This paper presents a simple yet effective method to analyze process variations using statistics on manufacturing in-line data without assuming any explicit underlying model for process variations. Our method is based on a variant of principal component analysis and is able to reveal systematic variation patterns existing on a die-to-die and wafer-to-wafer level individually. The separation of die variation from wafer variation can enhance the understanding of a nature of the process uncertainty. Our case study based on the proposed decomposition method shows that the dominating die-to-die variation and wafer-to-wafer variation represent 31% and 25% of the total variance of a large set of in-line parameters in 65nm SOI CMOS technology

A complementary LC-VCO is integrated in a 65nm SOI process and is statistically characterized on a 300mm wafer. Average center frequency is 67.9GHz and frequency tuning range is 6.14GHz or 9.05%. It achieves a phase noise of -106dBc/Hz at 10MHz offset and consumes 5.37mW from a 1.2V supply. The VCO yield is 94.7% for 70GHz operation.

A static CML divide-by-2 frequency divider is integrated in 65nm SOI CMOS. The maximum operating frequency is 90GHz while dissipating 52.4mW. The self-oscillation frequency is 92GHz with 0.57pJ switching energy. Measurement of self-oscillation frequency at multiple bias conditions enables estimation of the variation in threshold voltage, capacitance, and resistance.

A stochastic data-trained method is presented that estimates and compensates for cloud perturbations of hyperspectral IR radiances. The RMS accuracy is ~0.2-0.4K for ~60 selected channels, and the algorithm is computationally efficient.

[1] A novel stochastic algorithm is presented for estimating Atmospheric Infrared Sounder (AIRS) radiances in the 3.7–15.4 micron spectral band that would be observed from space in the absence of clouds. This algorithm examines 3 × 3 sets of 15-km AIRS fields of view, selects the clearest fields, and then estimates a single cloud-cleared infrared spectrum for the 3 × 3 set using a series of simple linear and nonlinear operations on both the infrared and companion Advanced Microwave Sounding Unit (AMSU) microwave channels. These instruments were launched on the NASA Aqua satellite in May 2002. The algorithm was both trained and tested within 70° of the equator using global numerical weather analyses generated by the European Center for Medium-range Weather Forecasts (ECMWF); these analyses were converted to radiances using the SARTA v1.05 equation of radiative transfer. The RMS differences between the AIRS 4- and 15-micron CO2-band observations and the corresponding ECMWF/SARTA radiances over nighttime ocean are ∼0.2–0.3 K for ∼60 selected channels with weighting functions peaking at tropospheric altitudes down to the surface for the best 28% of all soundings selected using only AIRS data. For a larger ensemble of 314 channels the corresponding range was 0.27–0.40 K. Latitudes 30–70° yielded RMS differences of 0.26–0.78 K over land at night for the same 314 channels. Mean differences were largely eliminated by training the estimates using independent global observations made on the same 3 test days, which were spaced over 2 months.

In recent years, synthetic aperture radars (SARs) have been used to detect man-made targets and to distinguish them from naturally occurring background. This paper continues development of a fundamental, physics-based approach to assessing the performance of SAR-based automatic target recognition (ATR) systems. A major thrust of this effort is to quantify the performance advantages that accrue when the recognition processor exploits the detailed signatures of the target's component reflectors, e.g., their specularity, their polarization properties, etc. Its purpose is to assess models developed from the electromagnetic scattering theory. New lower and upper bounds on the probability of correct classification (PCC) are developed for targets composed of a constellation of geometrically-simple reflectors. The performance discrepancy of a conventiional full-resolution processor with respect to an optimal whitening-filter processor is discussed.© (2001) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.