424 results on '"Christer Svensson"'
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2. A scalable custom simulation machine for the Bayesian Confidence Propagation Neural Network model of the brain.
3. Low-Power and Low-Voltage Communication for SoCs
4. Resource efficient implementation of a 10Gb/s radio receiver baseband in FPGA.
5. A +32 dBm 1.85 GHz class-D outphasing RF PA in 130nm CMOS for WCDMA/LTE.
6. Envelope detector sensitivity and blocking characteristics.
7. Power consumption bounds for SAR ADCs.
8. A Class-D outphasing RF amplifier with harmonic suppression in 90nm CMOS.
9. A 2.4 GS/s, 4.9 ENOB at Nyquist, single-channel pipeline ADC in 65nm CMOS.
10. Power Consumption of Integrated Low-Power Receivers.
11. 2.6 Gb/s over a four-drop bus using an adaptive 12-tap DFE.
12. Multiband direct RF-sampling receiver front-end for WLAN in 0.13 μm CMOS.
13. 3-Gb/s, Single-ended Adaptive Equalization of Bidirectional Data over a Multi-drop Bus.
14. A 1.4V 25mW Inductorless Wideband LNA in 0.13μm CMOS.
15. A 3Gb/s/wire Global On-Chip Bus with Near Velocity-of-Light Latency.
16. An on-chip delay- and skew-insensitive multicycle communication scheme.
17. A high-level dynamic-error model of a pipelined analog-to-digital converter.
18. Synchronous latency-insensitive design for multiple clock domain.
19. An Extended Transition Energy Cost Model for Buses in Deep Submicron Technologies.
20. A new mesochronous clocking scheme for synchronization in SoC.
21. 2 GB/S decision feedback equalizer in 3.3 V 0.35 µM CMOS.
22. Timing closure through a globally synchronous, timing partitioned design methodology.
23. Bitline leakage equalization for sub-100nm caches.
24. A 1.6 GHz downconversion sampling mixer in CMOS.
25. Full-custom vs. standard-cell design flow: an adder case study.
26. Ultra Low Power Wake-Up Radio Using Envelope Detector and Transmission Line Voltage Transformer.
27. A 1 GHz linearized CMOS track-and-hold circuit.
28. Application of Knowledge-based System in a B-to-B Environment.
29. Modeling of dynamic errors in algorithmic A/D converters.
30. A Comparison between endonasal and external Dacryocystorhinostomy using the Lac-Q questionnaire
31. Design and Analysis of a Class-D Stage With Harmonic Suppression.
32. Analysis of a 5.5-V Class-D Stage Used in +30-dBm Outphasing RF PAs in 130- and 65-nm CMOS.
33. Low power mixed analog-digital signal processing.
34. GLMC: interconnect length estimation by growth-limited multifold clustering.
35. A 2.4 GS/s, Single-Channel, 31.3 dB SNDR at Nyquist, Pipeline ADC in 65 nm CMOS.
36. A novel mixed analog/digital MAC unit implemented with SC technique suitable for fully programmable narrow-band FIR filter applications.
37. A leakage-tolerant multi-phase keeper for wide domino circuits.
38. High speed interface for system-on-chip design by self-tested self-synchronization.
39. High speed multistage CMOS clock buffers with pulse width control loop.
40. Methodology of layout based schematic and its usage in efficient high performance CMOS design.
41. Power Dissipation Bounds for High-Speed Nyquist Analog-to-Digital Converters.
42. Low power and low voltage CMOS digital circuit techniques.
43. Separation and extraction of short-circuit power consumption in digital CMOS VLSI circuits.
44. Self-Synchronized Vector Transfer for High Speed Parallel Systems.
45. Efficient High-Speed CMOS Design by Layout Based Schematic Method.
46. A low-swing single-ended L1 cache bus technique for sub-90nm technologies.
47. Well-behaved global on-chip interconnect.
48. A 2.4-GHz RF sampling receiver front-end in 0.18-μm CMOS.
49. 5.8Gb/s 16: 1 Multiplexer and 1: 16 Demultiplexer Using 1.2µm BiCMOS.
50. System Level Policies for Fault Tolerance Issues in the FERMI Project.
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